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1 ? 2005 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-6358/5 october 2005 2.5v sequential flow-control device 48 bit wide configuration for use with 128mb to 256mb ddr sdram idt and the idt logo are trademarks of integrated device technology, inc commercial and industrial temperature ranges idt72t6480 features ? product to be used with single or multiple external ddr sdram to provide significant storage capability of up to 1gb density 133mhz operation (7.5ns read/write cycle time) user selectable input and output port bus-sizing - x48in to x48out - x48in to x24out - x48in to x12out - x24in to x48out - x24in to x24out - x24in to x12out - x12in to x48out - x12in to x24out - x12in to x12out for other bus configurations see idt72t6360 (x9, x18, or x36) 2.5v-lvttl or 3.3v-lvttl configured ports independent and simultaneous read and write access user selectable synchronous/asynchronous read and write port timing idt standard mode or fwft mode of operation empty and full flags for monitoring memory status programmable almost-empty and almost-full flags, each flag can default to one of four preselected offsets or serially programmed to a specific value selectable synchronous/asynchronous timing modes for almost-empty and almost-full flags master reset clears all data and settings ? ? ? ? ? partial reset clears data, but retains programmable settings ? ? ? ? ? depth expandable with multiple devices for densities greater than 1gb ? ? ? ? ? width expandable with multiple devices for bus widths greater than 36 bits ? ? ? ? ? jtag functionality (boundary scan) ? ? ? ? ? available in a 324-pin pbga, 1mm pitch, 19mm x 19mm ? ? ? ? ? high performance 0.18 m cmos technology ? ? ? ? ? industrial temperature range (-40 c to +85 c) is available ? ? ? ? ? supports industry standard ddr specifications, including samsung, micron, and infineon memories functional block diagram 36-bits 36-bits 36-bits 6358 drw01 x48, x24, or x12 high density ddr sdram x16, x32, x36, or x64 128mb to 256mb 64 ddr sdram control logic x48, x24, or x12 idt72t6480 sequential flow control device data addr ck ck we cas ras flag logic jtag control (boundary scan) fwft fsel[1:0] ff / ir paf pae write control logic read control logic reset logic mrs prs i/o bus configuration iosel bm[3:0] wen wclk/wr ren rclk/rd rcs input register ef / or output register wcs asyw mclk asyr dqs tck/sclk tms tdo/so tdi/si 13 8
2 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 table of contents features ............................................................................................................................... .......................................................................................... 1 description ............................................................................................................................... ....................................................................................... 4 pin configuration ............................................................................................................................... .............................................................................. 6 pin descriptions ............................................................................................................................... ........................................................................... 7-10 - read port interface .......................................................................................................... ................................................................................. 7 - write port interface ............................................................................................................................... ............................................................. 7 - memory interface ............................................................................................................. ................................................................................. 8 - control and feature interfa ce ................................................................................................ ............................................................................ 8 - power and ground signals ..................................................................................................... ........................................................................ 10 - pin number location table .................................................................................................... .......................................................................... 10 detailed descriptions ............................................................................................................................... ...................................................................... 11 functional descriptions ............................................................................................................................... ................................................................... 22 signal descriptions ............................................................................................................................... ......................................................................... 23 device characteristics ............................................................................................................................... .................................................................... 27 ac test conditions ............................................................................................................................... ......................................................................... 29 ac electrical characteristics ............................................................................................................................... ............................................................ 30 jtag timing specifications ............................................................................................................................... ............................................................. 45 depth expansion configuration ............................................................................................................................... ...................................................... 49 width expansion configuration ............................................................................................................................... ....................................................... 50 ordering information ............................................................................................................................... ....................................................................... 51 list of tables table 1 ? ddr sdram minimum specifications ............................................................................................................................... .............................. 11 table 2 ? supported memory vendors ............................................................................................. ............................................................................. 11 table 3 ? total possible external memory configurations ........................................................................ ....................................................................... 12 table 4 ? sfc to ddr sdram interface connections ............................................................................... .................................................................... 14 table 5 ? total useable memory based on various configurations ................................................................. .................................................................. 18 table 6 ? idt72t6480 maximum frequency based on 166mhz ddr sdram ............................................................... ............................................. 19 table 7 ? idt72t6480 maximum frequency based on 133mhz ddr sdram ............................................................... ............................................. 19 table 8 ? mic[2:0] configurations .............................................................................................. .................................................................................... 20 table 9 ? memory configurations settings ....................................................................................... .............................................................................. 21 table 10 ? device configuration ................................................................................................ ..................................................................................... 22 table 11? default programmable flag offsets ............................................................................................................................... .................................. 22 table 12? number of bits required for offset registers ............................................................................................................................... ................... 22 table 13 ? bus-matchings ....................................................................................................... ...................................................................................... 24 table 14 ? mtype[1:0] configurations ........................................................................................... ............................................................................... 25 table 15 ? parameters af fected by i/o selection ................................................................................ ............................................................................. 25
3 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 list of figures figure 1. sequential flow-control device block diagram ......................................................................... ....................................................................... 5 figure 2a. configuration 1 - two chip solution ................................................................................. ............................................................................. 13 figure 2b. configuration 2 - two chip solution ................................................................................. ............................................................................. 13 figure 2c. configuration 3 - three chip solution ............................................................................... ............................................................................ 13 figure 2d. configuration 4 - three chip solution ............................................................................... ............................................................................ 13 figure 2e. configuration 5 - three chip solution ............................................................................... ............................................................................ 13 figure 2f. configuration 6 - four chip solution ................................................................................ .............................................................................. 13 figure 2g. configuration 7 - five chip solution ................................................................................ .............................................................................. 13 figure 3. memory interface connection (single chip) ............................................................................ ........................................................................ 17 figure 4. memory interface connection (two chip) ............................................................................... ........................................................................ 17 figure 5a. ac t est load ........................................................................................................ ........................................................................................ 29 figure 5b. lumped capacitive load, typical derating ............................................................................ ....................................................................... 29 figure 6. master reset and initialization ............................................................................................................................... .......................................... 32 figure 7. partial reset ........................................................................................................ ........................................................................................... 33 figure 8. write first word cycles - idt standard mode .......................................................................... ....................................................................... 34 figure 9. write first word cycles - fwft mode .................................................................................. .......................................................................... 34 figure 10. empty boundary - idt standard mode .................................................................................. ...................................................................... 35 figure 11. empty boundary - fwft mode .......................................................................................... .......................................................................... 35 figure 12. full boundary - idt standard mode ................................................................................... ......................................................................... 36 figure 13. full boundary - fwft mode ........................................................................................... ............................................................................ 36 figure 14. output enable ....................................................................................................... ........................................................................................ 37 figure 15. read chip select .................................................................................................... ..................................................................................... 37 figure 16. write chip select ................................................................................................... ....................................................................................... 37 figure 17. bus-matching configuration - x48 in to x24 out - idt standard mode .................................................. ........................................................ 38 figure 18. bus-matching configuration - x48 in to x12 out - idt standard mode .................................................. ........................................................ 38 figure 19. bus-matching configuration - x24 in to x48 out - idt standard mode .................................................. ........................................................ 39 figure 20. bus-matching configuration - x12 in to x48 out - idt standard mode .................................................. ........................................................ 39 figure 21. synchronous pae flag - idt standard mode and fwft mode ........................................................................................ ........................... 40 figure 22. synchronous paf flag - idt standard mode and fwft mode ........................................................................................ ........................... 40 figure 23. asynchronous read and paf flag - idt standard mode .................................................................. ........................................................... 41 figure 24. asynchronous write and pae flag - idt standard mode ................................................................. ............................................................. 41 figure 25. asynchronous write and paf flag - idt standard mode ................................................................. ............................................................. 41 figure 26. asynchronous empty boundary - idt standard mode ..................................................................... ............................................................. 42 figure 27. asynchronous full boundary - idt standard mode...................................................................... ................................................................ 42 figure 28. asynchronous read and pae flag - idt standard mode ...................................................................................................... ...................... 42 figure 29. serial loading of programmable flag registers (idt standard and fwft modes) ......................................... ............................................. 43 figure 30. reading of programmable flag registers (idt standard and fwft modes) ................................................ ............................................... 43 figure 31. standard jt ag t iming ............................................................................................... .................................................................................. 44 figure 32. jtag architecture ............................................................................................................................... .......................................................... 45 figure 33. tap controller state diagram ........................................................................................ ............................................................................... 46 figure 34. depth expansion configuration in idt standard mode .................................................................. ............................................................... 49 figure 35. depth expansion configuration in fwft mode .......................................................................... .................................................................. 49 figure 36. width expansion configuration in idt standard mode and fwft mode .................................................... ................................................... 50
4 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 description the idt72t6480 sequential flow-control device is a device incorporating a seamless connection to external ddr sdram for significant storage capacity supporting high-speed applications. both read and write ports of the sequential flow-control can operate independently at up to 133mhz. there is a user selectable correction feature that will correct any erroneous single data bit when reading from the sdram. the independent read and write ports each has associated read and write clocks, enables, and chip selects. both ports can operate either synchro- nously or asynchronously. other features include bus-matching, program- mable status flags with selectable synchronous/asynchronous timing modes, idt standard or fwft mode timing, and jtag boundary scan functionality. the bus-matching feature will allow the inputs and outputs to be configured to x48, x24, or x12 bus width. there are four default offset values available for the programmable flags ( pae / paf ), as well as the option of serially programming the offsets to a specific value. the device package is 19mm x 19mm 324-pin pbga. it operates at a 2.5v core voltage with selectable 2.5v or 3.3v i/os. the i/o interface to the sdram will be 2.5v sstl_2 only and not 3.3v tolerant. both industrial and commercial temperature ranges will be offered. the sequential flow-control device controls individual ddr sdram of either 128mb or 256mb. the device will support industry standard ddr specification memories (note ddr ii is not supported), which include vendors such as samsung, micron, and infineon. the data bus connected to the ddr sdram can be 16-bit, 32-bit, or 64-bits wide. the sequential flow-control device can independently control up to four separate external memories for a maximum of density of 1gb (128mb). depth expansion mode is available for applications that require more than 1gb of storage memory.
5 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 multi-clock arbitration circuits logic control circuits state machine memory interface refresh counter qp cache control logic d[47:0] 48 input register output register q[47:0] 48 48 48 input bus-matching logic output bus-matching logic 144 144 144 qp cache 72 x 36 qp cache 72 x 36 72 optional bypass 72 72 optional bypass 72 check bit generator 72 72 error detection correction optional bypass 72 72 optional bypass 72 72 72 check bit generator error detection correction memory interface data and bus-matching 8 64 dq[63:0] dqs[7:0] dll pll tms tdi tck tdo jtag memory interface address and control ras cas we ba[1:0] addr[12:0] 13 72 6358 drw02 144 mclk ck ck dq[63:0] dqs[7:0] figure 1. sequential flow-control device block diagram
6 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 pin configuration pbga (bb324-1, order code: bb) top view a b c d e f g h j k l m n p r t d36 bm2 bm1 mtype0 mspeed idem d33 q30 q36 swen paf q35 q41 q45 q46 d38 fsel0 d45 mic1 ff / ir tdi/si q42 q34 gnd gnd dq14 dq19 dqs3 d31 dq9 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a5 a10 we ras d5 dqs5 12 34 56 78 910111213141516 a1 ball pad corner a0 dq5 d10 d15 d20 d25 d30 a9 ba1 mclk d4 d11 d16 d21 d26 dq13 dq15 dq31 d12 d3 d17 d22 d27 d32 q31 q1 q5 q12 q11 q15 q19 dqs4 dq44 dq39 dq17 d0 dqs1 dq2 ck dq12 dq3 dq6 ba0 a2 a11 a6 dq47 dq34 dq41 dq37 avcc dq7 dq0 dqs0 a12 a3 a8 a7 dq46 cas dq43 dq33 q6 q7 q13 q28 q29 q33 q2 d1 d6 d9 d19 d14 d24 d29 dq10 dq45 v ref dq16 avcc a4 dq11 6358 drw03 u v gnd bm0 rclk/ rd mtype1 wclk/ wr q37 q38 sren rcs q40 q44 ef / or pae mic2 oe q43 q39 17 18 q22 q24 q27 q26 gnd gnd gnd dq57 q21 q0 q4 q9 q14 q17 q18 gnd dq49 dq51 q3 q8 q10 q16 q20 q25 dq63 dq50 dqs6 gnd gnd gnd gnd agnd v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc gnd gnd gnd gnd gnd v cc v cc v cc v cc v cc d23 v cc v cc v cc v ddq q23 v ddq v ddq v cc d18 gnd v ddq gnd v ddq bm3 v cc iosel q47 fsel1 d28 mic0 tdo/so jsel q32 gnd v cc d2 gnd v cc d7 gnd v cc d8 v cc v cc d13 gnd v ddq v ddq gnd v ddq v ddq gnd v ddq v ddq gnd v ddq v ddq d37 d39 gnd gnd d42 gnd d44 d47 mrs wen d43 prs d40 d41 asyw wcs tms tck/ sclk asyr d46 fwft ren dq8 dq4 dq1 ck a1 dq35 dq36 dq38 dq40 dq32 gnd gnd dq18 dqs2 dq20 dq21 agnd v cc v cc v cc v cc dq54 dq42 dq52 dq53 dq48 dq58 dq59 dq56 dq55 dq23 dq22 dq24 dq25 dq26 dq27 dq28 dq29 dq30 v cc v cc v cc v cc v cc dq60 dq62 dqs7 dq61 d31 d35 d34
7 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 read port interface asyr (1) v6 asynchronous input a high on this input during master reset will select synchronous read operation for the read port 3.3v or output port. a low will select asynchronous operation. if asynchronous is selected the 2.5v lvttl device must operate in idt standard mode and the read enable must be tied to gnd. ef / or v13 empty flag/ output in idt standard mode, the ef function is selected. ef indicates whether or not the device output ready 3.3v or memory is empty. in fwft mode, the or function is selected. or indicates whether or not 2.5v lvttl there is valid data available at the outputs. oe u12 output enable input asynchronous three-state control of the data outputs. all data outputs q[47:0] will be placed 3.3v or in high-impedance if this pin is high. conversely, all data outputs will be active when this 2.5v lvttl pin is low. pae u13 programmable output this is the programmable almost empty flag that can be used as an early indicator for the almost empty flag 3.3v or empty boundary condition of the internal memory. pae goes low if the number of words 2.5v lvttl in the sequential flow-control device is less than offset n, which is stored in the empty offset register. pae goes high if the number of words in the sequential flow-control device is greater than or equal to the offset n. q[47:0] see pin data output bus output data outputs for a 48, 24, and 12-bit bus. no. table 3.3v or 2.5v lvttl rclk/ v9 read clock/ input this is a dual function pin. if synchronous operation of the read port is selected, the rising rd read strobe 3.3v or edge of rclk reads data from the sequential flow-control device when ren is enabled. 2.5v lvttl if asynchronous operation of the read port is selected, a rising edge on rd reads data from the sequential flow-control device without the need of a free-running input read clock. rcs v12 read chip select input synchronous three-state control of the data outputs. provides another means of controlling 3.3v or the data outputs synchronous to rclk. can be regarded as a second out put enable signal. 2.5v lvttl ren v10 read enable input ren enables rclk for reading data from the sequential flow-control device. if 3.3v asynchronous mode is selected on the read port, this signal should be tied to gnd. 2.5v lvttl sren v11 serial read enable input when sren is brought low before the rising edge of sclk, the contents of the pae and 3.3v or paf offset registers are copied to a serial shift register. while sren is maintained low, on 2.5v lvttl each rising edge of sclk, one bit of data is shifted out of this serial shift register through the so output pin used only when jsel = 0. write port interface asyw (1) t6 asynchronous input a high on this input during master reset will select synchronous write operation for the write port 3.3v or input port. a low will select asynchronous operation. if asynchronous is selected the 2.5v lvttl device must operate in idt standard mode and the write enable must be tied to gnd. d[47:0] see pin data inputs input data inputs for a 48, 24, and 12-bit bus. no. table 3.3v or 2.5v lvttl ff / ir r12 full flag/ output in idt standard mode, the ff function is selected. ff indicates whether or not the device input ready 3.3v or memory is full. in fwft mode, the ir function is selected. ir indicates whether or not there 2.5v lvttl is space available for writing to the device memory. paf t12 programmable output this is the programmable almost full flag that can be used as an early indicator for the full almost full flag 3.3v or boundary condition of the internal memory. paf goes high if the number of free locations 2.5v lvttl in the sequential flow-control device is more than offset m, which is stored in the full offset register. paf goes low if the number of free locations in the sequential flow-control device is less than or equal to the offset m. swen t11 serial write enable input on each rising edge of sclk when swen is low, data from the si pin is serially loaded 3.3v or into the pae and paf registers used only when jsel = 0. 2.5v lvttl pin descriptions symbol pin no. name i/o type description location
8 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 pin descriptions (continued) symbol pin no. name i/o type description location write port interface (continued) wclk/wr v8 write clock/ input this is a dual function pin. if synchronous operation of the write port is selected, the rising write strobe 3.3v or edge of wclk writes data into the sequential flow-control device when wen is enabled. 2.5v lvttl if asynchronous operation of the write port is selected, a rising edge on wr writes data into the sequential flow-control device without the need of a free-running input write clock. wcs t7 write chip select input synchronous three-state control of the data inputs. provides a means of controlling the 3.3v or data inputs synchronous to wclk. typically used to avoid bus-contention when multiple 2.5v lvttl devices are sharing the same input data bus. wen v7 write enable input wen enables wclk for writing data into the sequential flow-control device. if 3.3v or asynchronous mode is selected on the write port, this signal should be tied to gnd. 2.5v lvttl memory interface a[12:0] see pin memory address output output address bus to be connected to the input address bus of the external memory to no. table bus sstl_2 provide row and column address. ba[1:0] ba1-b11 memory bank output address bits to be connected to the external memory's ba inputs to determine which bank ba0-c11 address input bit sstl_2 an active, read, write, or precharge command is being applied. ck c7 memory clock output clock output to be connected to the external memory's input clock. sstl_2 ck a7 memory clock output differential clock output to be connected to the external memory's differential input clock. inverted sstl_2 cas d12 memory column output output enable signal to be connected to the external memory's cas pin to activate and address strobe sstl_2 deactivate the column address strobe. dq[63:0] see pin memory data bus bi-directional input/ou tput data bus for the external memory's data bus. no. table sstl_2 dqs[7:0] see pin memory data bi-directional input/output data strobe to be connected to the external memory's data strobe. no. table strobe sstl_2 ras a12 memory row output output strobe signal to be connected to the external memory's ras pin to activate and address strobe sstl_2 deactivate the row address strobe. we a11 memory write output output strobe signal to be connected to the external memory's we pin to activate and enable sstl_2 deactivate the write address strobe. control and feature interface bm[3:0] (1) see pin bus-matching bit input selects the bus width of the read and write ports. no. table 3.3v or 2.5v lvttl fsel[1:0] (1) fsel1-p6 flag select bit input during master reset, these inputs will select one of four default values for the programmable fsel0-r6 3.3v or flags pae and paf . the selected value will apply to both pae and paf offset. 2.5v lvttl fwft (1) u7 first word fall input during master reset, a high on this input selects fwft timing mode. a low selects idt through 3.3v or standard timing mode. 2.5v lvttl idem (1) r7 idt standard mode input this select pin is used for depth expansion configuration in idt standard mode. if this pin depth expansion 3.3v or is tied high, then the ff / ir signal will be inverted to provide a seamless depth mode select 2.5v lvttl expansion interface. if depth expansion in fwft mode is desired, this pin should be tied to gnd. if no depth expansion is used, this pin should be tied to gnd. iosel (1) p7 i/o v ddq select input this input determines whether the inputs and outputs will tolerate a 2.5v or 3.3v voltage 3.3v or signals. if iosel is high, then all i/os will be 2.5v tolerant. if iosel is low, then all i/os 2.5v lvttl will be 3.3v tolerant. see table 15, for a list of affected i/o signals.
9 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 pin descriptions (continued) symbol pin no. name i/o type description location control and feature interface (continued) jsel (1) p11 jtag select input this pin selects whether the jtag pins will be used for serial programming. if jsel is 3.3v or high, the jtag pins will only be used for jtag boundary-scan function. if jsel is low, 2.5v lvttl the jtag function is disabled and the jtag pins will be used for serial programming of the pae / paf offset registers. mic[2:0] (1) mic2-u10 memory input these signals enable the edc feature of the device. see table 8, mic[2:0] configurations mic1-r10 configuration 3.3v or for details. mic0-p10 2.5v lvttl mclk h1 master clock input 33mhz reference clock used to generate ck and ck for external memory interface. 3.3v or 2.5v lvttl mrs v5 master reset input master reset initializes the read and write pointers to zero and sets the output register to all 3.3v or zeros. all initialized settings for the device will be configured during master reset. 2.5v lvttl mspeed (1) t8 memory speed input this input select the speed of the external memory interfacing the sequential flow-control 3.3v or device. a low selects 133mhz, and high selects 166mhz. 2.5v lvttl mtype (1) mtype1-u8 memory type input these inputs select which type of external memory is interfacing the sequential flow-control [1:0] mtype0-r8 [1:0] 3.3v or device. see table 14 for the list of selectable memories. 2.5v lvttl prs u6 partial reset input partial reset initializes the read and write pointers to zero and sets the output registers to all 3.3v or zeros. all existing configurations in the sequential flow-control device will not be affected. 2.5v lvttl this includes the idt standard or fwft mode timing, programmable flag settings, and bus width and data rate mode. tck/ u11 jtag clock/ input this is a dual function pin. when the jsel pin is high, this is the clock input for jtag boundary- sclk serial clock 3.3v or scan function. one of four terminals required by ieee standard 1149.1-1990. test operations 2.5v lvttl of the device are synchronous to tck. data from tms and tdi are sampled on the rising edge of tck and outputs change on the falling edge of tck. when the jsel pin is low, this is the serial clock input for writing and reading the pae / paf offset registers. on the rising edge of every sclk when swen is low, one bit of data from the si pin is shifted into the pae and paf offset registers. on the rising edge of each sclk when sren is low, one bit of data from the so pin is shifted out of the pae and paf offset registers. if the jtag or serial programming is not used this signal needs to be tied to gnd. tdi/si r11 jtag test data input this is a dual function pin. when the jsel pin is high, this is the jtag test data input pin. one input/ serial input 3.3v or of four terminals required by ieee standard 1149.1-1990. during the jtag boundary scan 2.5v lvttl operation, test data serially loaded via the tdi on the rising edge of tck to the instruction register, id register and bypass register. when the jsel pin is low, this is the serial input pin for the pae / paf offset registers. an internal pull-up resistor forces tdi/si high if left unconnected. tdo/so p12 jtag test data output this is a dual function pin. when the jsel pin is high, this is the jtag test data output pin. output/serial output 3.3v or one of four terminals required by ieee standard 1149.1-1990. during the jtag boundary 2.5v lvttl scan operation, test data serially loaded output via the tdo on the falling edge of tck from either the instruction register, id register and bypass register. this output is high-impedance except when shifting, while in shift-dr and shift-ir controller states. when the jsel pin is low, this is the serial data output pin for the pae / paf offset registers. tms t10 jtag mode select input tms is a serial input pin. one of four terminals required by ieee standard 1149.1-1990. tms 3.3v or directs the device through its tap controller states. an internal pull-up resistor forces tms high 2.5v lvttl if left unconnected. please see next page for power & ground pins and pin number location table. note: 1. these pins should not change after master reset.
10 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 pin number location table symbol name i/o type pin number a[12:0] memory address output a12-d11, a11-c10, a10-b10, a9-a10, a8-d10, a7-d9, a6-c9, a5-a9, a4-b9, a3-d8, a2-c8, a1-a8, a0-b8 bus sstl_2 bm[3:0] bus-matching input bm3-p9, bm2-r9, bm1-t9, bm0-u9 3.3v or 2.5v lvttl d[47:0] data inputs input d47-v4, d46-u5, d45-r5, d44-v3, d43-u4, d42-u3, d41-t5, d40-t4, d39-t3, d38-r4, d37-t2, 3.3v or d36-t1, d35-r2, d34-r1, d33-r3, d32-p2, d31-p1, d30-p3, d29-p4, d28-p5, d27-n2, d26-n1, 2.5v lvttl d25-n3, d24-n4, d23-n5, d22-m2, d21-m1, d20-m3, d19-m4, d18-m5, d17-l2, d16-l1, d15-l3, d14-l4, d13-l5, d12-k2, d11-k1, d10-k3, d9-k4, d8-k5, d7-j5, d6-j4, d5-j3, d4-j1, d3-j2, d2-h5, d1-h4, d0-h3 dq[63:0] memory data bus bi-directional dq63-h17, dq62-g15, dq61-g16, dq60-g18, dq59-f14, dq58-f15, dq57-f18, dq56-f17, sstl_2 dq55-f16, dq54-e15, dq53-e18, dq52-e17, dq51-d17, dq50-c18, dq49-c17, dq48-e16, dq47-c15, dq46-d15, dq45-c16, dq44-b15, dq43-d14, dq42-e14, dq41-c14, dq40-a16, dq39-b14, dq38-a15, dq37-c13, dq36-a14, dq35-a13, dq34-c12, dq33-d13, dq32-b12, dq31-h2, dq30-g5, dq29-g4, dq28-g3, dq27-g2, dq26-f5, dq25-f4, dq24-f3, dq23-f1, dq22-f2, dq21-e5, dq20-e4, dq19-e1, dq18-e2, dq17-d3, dq16-d1, dq15-d2, dq14-c1, dq13-c2, dq12-c4, dq11-c3, dq10-a3, dq9-b4, dq8-a4, dq7-d4, dq6-c5, dq5-b5, dq4-a5, dq3-c6, dq2-b6, dq1-a6, dq0-d6, dqs[7:0] memory data bi-directional dqs7-g17, dqs6-d18, dqs5-b16, dqs4-b13, dqs3-g1, dqs2-e3, dqs1-b3, dqs0-d5 strobe sstl_2 q[47:0] data outputs output q47-p13, q46-r13, q45-t13, q44-v14, q43-u14, q42-r14, q41-t14, q40-v15, q39-u15, q38-v16, 3.3v or q37-u16, q36-t16, q35-t15, q34-r15, q33-p15, q32-p14, q31-p16, q30-r16, q29-n15, q28-m15, 2.5v lvttl q27-t17, q26-r17, q25-p17, q24-t18, q23-n14, q22-r18, q21-p18, q20-n17, q19-n16, q18-n18, q17-m18, q16-m17, q15-m16, q14-l18, q13-l15, q12-k16, q11- l16, q10-l17, q9-k18, q8-k17, q7-k15, q6-j15, q5-j16, q4-j18, q3-j17, q2-h15, q1-h16, q0-h18 v cc core v cc & output power e(8-13), f(6-13), g(6,7,12-14), h6, j6, k6, l(6,7), m(6-8), n(6-11), p8 voltage for ddr sdram v ddq output rail voltage for power h(13,14), j(13,14), k(13,14), l(13,14), m(12-14), n(12,13) i/os gnd ground pin ground a(1,2,17,18), b(1,2,17,18), g(8-11), h(7-12), j(7-12), k(7-12), l(8-12), m(9-11), u(1,2,17,18), v(1,2,17,18) power and ground signals v cc see pin core v cc and power the core power supply pins for the device as well as to the external ddr sdram. no. table output voltage needs to be connected to a +2.5v v cc power plane. for ddr sdram av cc b7, d7 internal pll v cc power the power supply pins for the internal pll of the device. needs to be connected to a +2.5v supply rail. v ddq see pin output rail voltage power this pin is used to provide power to the output drivers. the nominal values are 2.5v or no. table for i/os 3.3v, depending on the state of the iosel pin. v ref d16 reference voltage power this is a voltage reference input to the sdram and must be connected to v cc/2 . gnd see pin table ground pin ground the ground pins for the device that must be connected to the ground plane. agnd e6, e7 ground pin for ground the ground pins for the analog circuitry in the device that must be connected to the ground analog circuit plane. pin descriptions (continued) symbol pin no. name i/o type description location
11 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 detailed descriptions sequential flow-control structure the idt sequential flow-control (sfc) device is comprised of three inter- faces: input port, output port, and memory interface. the input and output port can operate independently of each other with selectable bus widths of x12, x24, or x48 bits wide. the third interface, or memory interface, is connected directly to an external memory, which can be used to offload data entering the sfc device. writing and reading from the sequential flow-control device writing into the sfc device is accomplished by setting the write enable signal ( wen ) and write chip select ( wcs ) low with a free running write clock (wclk). data will be written on the rising edge of every wclk into the quad-port (qp) cache of the sfc device. the internal state machine of the device will determine whether to send the data to the ddr sdram or send it directly through to the output bus, depending on when the data is to be accessed. this provides ?data coherency? and minimizes the path that the data has to travel. reading from the sfc device is accomplished by setting the read enable signal ( ren ) and read chip select ( rcs ) low with a free running read clock (rclk). data will be sent to the output bus on the rising edge of every rclk. this data will be accessed either from the qp cache or the external ddr sdram. external memory selection the ddr sdram interface of the sfc device can support ddr sdram with standard ddr i specifications. the sfc device can support any external memory within the following characteristics: ? bus width: 16-bit or 32-bit wide ? speed: 133mhz or 166mhz ? density: 128mb or 256mb table 1 lists the ddr sdram minimum specifications that are required to meet the sequential flow-control device requirements. table 2 lists the memory vendors and associated part numbers of ddr sdrams that have been validated by idt to meet the requirements for the ddr sdram interface. ddr sdram minimum specifications symbol parameter 16-bit ddr 32-bit ddr units sdram sdram t ck cl = 2.5 clock cycle time 6 n/a ns cl = 3.0 n/a 6 t rfc auto refresh command period 75 63 ns t rcd active to read/write delay 20 n/a ns t rp precharge comman period 20 18 ns t wr write recovery time 15 1.5 ns t rcdrd active to read delay n/a 18 ns t rcdwr active to write delay n/a 9 ns table 1 ? ddr sdram minimum specifications density bus width vendor p art# 128mb 32 samsung k4d263238"x"-gc45 256mb 16 samsung k4h561638"x"-tclb3 k4h561638"x"-gclb3 256mb 16 micron mt46v16m16tg-6t mt46v16m16tg-75 256mb 16 infineon hyb25d256160btl-6 hyb25d256160btl-7 256mb 32 samsung k4d553238"x"-jc50 table 2 ? supported memory vendors notes : 1. the part numbers listed above include packages that are recommended and validated by idt. other packages (such as lead free pcb, fbga, etc.) may also be used but have not been validated by idt. 2. the letter "x" for samsung memory part numbers denotes the latest die revision for that particular device. check with samsung for the latest updated part number. note : 1. these are the minimum specifications that the ddr sdram must meet.
12 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 two chip solution (1) three chip solution (1) four chip solution (1) five chip solution (1) (2) configuration 1, 2 (2) configurations 3, 4, 5 (2) configuration 6 (2) configuration 7 1 x128mb [4m x 32] 2 x 128mb [4m x 32] n/a n/a total memory: 128mb total memory: 256mb 1 x 256mb [8m x 32] 2 x 256mb [8m x 32] n/a n/a total memory: 256mb total memory: 512mb 1 x 128mb [8m x 16] 2 x 128mb [8m x 16] 3 x 128mb [8m x 16] 4 x 128mb [8m x 16] total memory: 128mb total memory: 256mb total memory: 384mb total memory: 512mb 1 x 256mb [16m x 16] 2 x 256mb [16m x 16] 3 x 256mb [16m x 16] 4 x 256mb [16m x 16] total memory: 256mb total memory: 512mb total memory: 768mb total memory: 1gb table 3 ? total possible external memory configurations external memory configurations the ddr sdram interface of the sequential flow-control (sfc) device has a 64-bit output data bus that provides up to four (16-bit sdram) external ddr sdram connections. for multiple memory connections, they must be of the same density configuration and speed grade. for example, two device connected cannot consist of one 128mb and one 256mb memory nor two 128mb with one at 100mhz and the other at 133mhz. below is a summary of the possible configurations: ? one 16-bit device connecting a x16 interface to the ddr sdram ? one 32-bit device connecting a x32 interface to the ddr sdram ? two 16-bit devices connecting a x32 interface to the ddr sdram ? two 32-bit devices connecting a x36 interface to the ddr sdram ? two 32-bit devices connecting a x64 interface to the ddr sdram ? three 16-bit devices connecting a x36 interface to the ddr sdram ? four 16-bit devices connecting a x64 interface to the ddr sdram these various configurations determine the storage density of the sfc device. the storage density can range from a minimum of 128mb to a maximum of 1gb. table 3 lists the possible ways to connect the ddr sdrams and the number of chipset solutions to obtain the various storage densities. notes: 1. the chip solution number includes the sequential flow-control device and external ddr sdram 2. see figure 2a-2g for the 7 different configurations referenced in the table above.
13 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 connecting the ddr sdram below are the various chipset solution configurations available to the sequential flow-control device (see figure 2a-2g). the external memory interface is designed to seamlessly connect one or more ddr sdrams. the output signal names should be connected directly to its corresponding input signal on the ddr sdram. there are three signals on the ddr sdram that must be tied to a static state. cke, cs , and dm. table 4 outlines how to connect the many interface pins to the ddr sdram(s). figure 3 and 4 are some examples of the memory interface connections for various density configura- tions. for information on ddr sdram layout recommendations, please see idt application note an-423. figure 2b (1) . configuration 2 - two chip solution ddr sdram: 256mb [16mb x 16] total memory density: 256mb useable memory (2) : 216mb figure 2c. configuration 3 - three chip solution ddr sdram: 128mb [4mb x 32] or 256mb [8mb x 32] total memory density: 256mb or 512mb useable memory (2) : 216mb or 504mb figure 2e (1) . configuration 5 - three chip solution ddr sdram: 256mb [16mb x 16] total memory density: 512mb useable memory (2) : 504mb figure 2f (1) . configuration 6 - four chip solution ddr sdram: 256mb [16mb x 16] total memory density: 768mb useable memory (2) : 567mb figure 2g (1) . configuration 7 - five chip solution ddr sdram: 256mb [16mb x 16] total memory density: 1gb useable memory (2) : 1008mb figure 2a. configuration 1 - two chip solution idt sfc 128mb or 256mb ddr sdram 6358 drw04 data bus 32 12 address bus ddr sdram: 128mb [4mb x 32] or 256mb [8mb x 32] total memory density: 128mb or 256mb useable memory (2) : 108mb or 252mb notes: 1. ? 12-bit address bus for 8mb x16 ? 13-bit address bus for 16mb x16 2. refer to total available memory usage section for details. idt sfc 256mb ddr sdram 6358 drw05 data bus 16 13 address bus 64 32 idt sfc 128mb or 256mb ddr sdram 6358 drw06 data bus 12 32 12 address bus 32 16 idt sfc 256mb ddr sdram 6358 drw08 data bus 13 16 13 address bus 4 36 13 idt sfc 256mb ddr sdram 6358 drw09 data bus 13 16 13 address bus 16 64 16 16 idt sfc 256mb ddr sdram 13 6358 drw10 data bus 13 address bus figure 2d. configuration 4 - three chip solution ddr sdram: 128mb [4mb x 32] or 256mb [8mb x 32] total memory density: 256mb or 512mb useable memory (2) : 108mb or 252mb 36 4 idt sfc 128mb or 256mb ddr sdram 6358 drw07 data bus 12 32 12 address bus
14 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 table 4 ? sfc to ddr sdram interface connections sfc outputs ddr sdram dq[31:0] dq[31:0] dqs[3:0] dqs[3:0] a[11:0] a[11:0] ck, ck ck, ck ras , cas ras , cas ba[1:0] ba[1:0] we we ddr sdram hard wired pins cke v cc cs gnd dm[3:0] gnd sfc hard wired pins dq[63:32] v cc dqs[7:4] v cc a12 v cc configuration 1 sfc outputs ddr sdram dq[15:0] dq[15:0] dqs0 ldqs dqs1 udqs a[12:0] a[12:0] ck, ck ck, ck ras , cas ras , cas ba[1:0] ba[1:0] we we ddr sdram hard wired pins cke v cc cs gnd ldm gnd udm gnd sfc hard wired pins dq[63:16] v cc dqs[7:2] v cc configuration 2 idt sfc 128mb or 256mb ddr sdram 6358 drw04 data bus 32 12 address bus idt sfc 256mb ddr sdram 6358 drw05 data bus 16 13 address bus sfc outputs ddr sdram #1 ddr sdram #2 dq[31:0] dq[31:0] -- dq[35:32] -- dq[3:0] dq[63:36] -- -- dqs[3:0] dqs[3:0] -- dqs[7:4] -- dqs[3:0] a[11:0] a[11:0] a[11:0] ck, ck ck, ck ck, ck ras , cas ras , cas ras , cas ba[1:0] ba[1:0] ba[1:0] we we we ddr sdram hard wired pins cke v cc cs gnd dm[3:0] gnd dq[31:4] v cc sfc hard wired pins a12 v cc configuration 4 36 4 idt sfc 128mb or 256mb ddr sdram 6358 drw07 data bus 12 32 12 address bus sfc outputs ddr sdram #1 ddr sdram #2 dq[31:0] dq[31:0] -- dq[63:32] -- dq[31:0] dqs[3:0] dqs[3:0] -- dqs[7:4] -- dqs[3:0] a[11:0] a[11:0] a[11:0] ck, ck ck, ck ck, ck ras , cas ras , cas ras , cas ba[1:0] ba[1:0] ba[1:0] we we we ddr sdram hard wired pins cke v cc cs gnd dm[3:0] gnd sfc hard wired pins a12 v cc configuration 3 64 32 idt sfc 128mb or 256mb ddr sdram 6358 drw06 data bus 12 32 12 address bus
15 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 table 4 ? sfc to ddr sdram interface connections(continued) sfc outputs ddr sdram #1 ddr sdram #2 dq[15:0] dq[15:0] -- dq[31:16] -- dq[15:0] dqs0 ldqs -- dqs1 udqs -- dqs2 -- ldqs dqs3 -- udqs a[12:0] a[12:0] a[12:0] ck, ck ck, ck ck, ck ras , cas ras , cas ras , cas ba[1:0] ba[1:0] ba[1:0] we we we ddr sdram hard wired pins cke v cc cs gnd ldm gnd udm gnd sfc hard wired pins dq[63:32] v cc dqs[7:4] v cc configuration 5 sfc outputs ddr sdram #1 ddr sdram #2 ddr sdram #3 dq[15:0] dq[15:0] -- -- dq[31:16] -- dq[15:0] -- dq[35:32] -- -- dq[3:0] dqs0 ldqs -- -- dqs1 udqs -- -- dqs2 -- ldqs -- dqs3 -- udqs -- dqs4 -- -- ldqs dqs5 -- -- udqs a[12:0] a[12:0] a[12:0] a[12:0] ck, ck ck, ck ck, ck ck, ck ras , cas ras , cas ras , cas ras , cas ba[1:0] ba[1:0] ba[1:0] ba[1:0] we we we we ddr sdram hard wired pins cke v cc cs gnd ldm gnd udm gnd dq[15:4] v cc sfc hard wired pins dq[63:36] v cc dqs[7:6] v cc configuration 6 32 16 idt sfc 256mb ddr sdram 6358 drw08 data bus 13 16 13 address bus 4 36 13 idt sfc 256mb ddr sdram 6358 drw09 data bus 13 16 13 address bus 16
16 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 sfc outputs ddr sdram #1 ddr sdram #2 ddr sdram #3 ddr sdram #4 dq[15:0] dq[15:0] -- -- -- dq[31:16] -- dq[15:0] -- -- dq[47:32] -- -- dq[15:0] -- dq[63:48] -- -- -- dq[15:0] dqs0 ldqs -- -- -- dqs1 udqs -- -- -- dqs2 -- ldqs -- -- dqs3 -- udqs -- -- dqs4 -- -- ldqs -- dqs5 -- -- udqs -- dqs6 -- -- -- ldqs dqs7 -- -- -- udqs a[12:0] a[12:0] a[12:0] a[12:0] a[12:0] ck, ck ck, ck ck, ck ck, ck ck, ck ras, cas ras, cas ras, cas ras, cas ras, cas ba[1:0] ba[1:0] ba[1:0] ba[1:0] ba[1:0] we we we we we ddr sdram hard wired pins cke v cc cs gnd ldm gnd udm gnd configuration 7 table 4 ? sfc to ddr sdram interface connections(continued) 64 16 16 idt sfc 256mb ddr sdram 13 6358 drw10 data bus 13 address bus
17 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 3. memory interface connection (single chip) 6358 drw11 cke v cc dm[3:0] cs ddr sdram 2m x 16 x 4 128m ck dqs[3:0] we cas ras dq[31:0] a[11:0] ck dqs[3:0] we cas ras dq[31:0] a[11:0] sequential flow-control device 4 32 12 ck ck figure 4. memory interface connection (two chip) 64 8 cke v cc dm[3:0] cs ck dqs[3:0] we cas ras dq[31:0] a[11:0] ck ddr sdram 8m x 32 256m ck dqs[7:0] we cas ras dq[31:0] a[11:0] sequential flow-control device ck 6358 drw12 cke v cc dm[3:0] cs ck dqs[3:0] we cas ras dq[31:0] a[11:0] 32 12 ck 12 4 32 12 4
18 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 total available memory usage the sequential flow-control (sfc) is designed to efficiently use as much of the ddr sdram memory as possible, but due to the discontinuity between the sfc bus width (x48) and the ddr sdram interface (x16 or x32), some columns in a row of the sdram will not be used. as a result, the total usable memory will be slightly less than the total available memory in the sdram. table 5 outlines the total usable memory for the various configurations depending on whether or not the error detection and correction (edc) feature is selected. if the edc feature is selected, 8 syndrome bits will be generated per every 64 bits of data. therefore every third write burst to the sdram will send out the 8 syndrome bits, resulting in 24 unused bits in the column. therefore, using the edc feature, there will be significantly less usable memory of data storage. the edc function is described in the error detection and correction section of this datasheet. total ddr sdram total usable total usable density memory (edc off) memory (edc on) configuration 1 1 x [4mb x 32] 128mb 108mb 72mb 1 x [8mb x 32] 256mb 252mb 144mb configuration 2 1 x [16mb x 16] 256mb 216mb 144mb configuration 3 2 x [4mb x 32] 256mb 216mb 144mb 2 x [8mb x 32] 512mb 504mb 288mb configuration 4 2 x [4mb x 32] 256mb 122mb 108mb 2 x [8mb x 32] 512mb 284mb 252mb configuration 5 2 x [8mb x 16] 256mb 252mb 144mb configuration 6 3 x [8mb x 16] 384mb 284mb 252mb 3 x [16mb x 16] 768mb 567mb 504mb configuration 7 4 x [16mb x 16] 1gb 1008mb 576mb table 5 ? total useable memory based on various configurations
19 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 table 6 ? idt72t6480 maximum frequency based on 166mhz ddr sdram maximum i/o operating frequency the sequential flow-control (sfc) device is designed to operate at the maximum frequency of 133mhz. there are certain configurations however, that can increase or decrease the maximum frequency of the input and output ports. in some configurations (e.g. x24 i/o width), the i/o speeds can run up to 166mhz. the main factors that determine the usable memory are the i/o bus- width of the sfc, the density and number of ddr sdrams connected, and whether or not edc is used. tables 6 and 7 lists the maximum frequency for the input and output ports of the sfc based on the various configurations. bus-width x48 bus-width x24 bus-width x12 edc on edc off edc on edc off edc on edc off configuration 1 50mhz 66mhz 100mhz 133mhz 166mhz 166mhz configuration 2 33mhz 33mhz 66mhz 66mhz 133mhz 133mhz configuration 3 100mhz 133mhz 166mhz 166mhz 166mhz 166mhz configuration 4 66mhz 66mhz 133mhz 133mhz 166mhz 166mhz configuration 5 50mhz 66mhz 100mhz 133mhz 166mhz 166mhz configuration 6 66mhz 66mhz 133mhz 133mhz 166mhz 166mhz configuration 7 100mhz 133mhz 166mhz 166mhz 166mhz 166mhz table 7 ? idt72t6480 maximum frequency based on 133mhz ddr sdram bus-width x48 bus-width x24 bus-width x12 edc on edc off edc on edc off edc on edc off configuration 1 33mhz 50mhz 66mhz 100mhz 133mhz 166mhz configuration 2 25mhz 25mhz 50mhz 66mhz 100mhz 133mhz configuration 3 66mhz 100mhz 133mhz 166mhz 166mhz 166mhz configuration 4 50mhz 50mhz 100mhz 100mhz 166mhz 166mhz configuration 5 33mhz 50mhz 66mhz 100mhz 133mhz 166mhz configuration 6 50mhz 50mhz 100mhz 100mhz 166mhz 166mhz configuration 7 66mhz 100mhz 133mhz 166mhz 166mhz 166mhz
20 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 error detection and correction the error detection and correction (edc) feature is available to ensure data integrity between the ddr sdram interface and the sfc. the edc corrects all single bit hard and soft errors that are accessed from the ddr sdram. multiple bit errors are not detected nor corrected. the edc logic blocks consist of a check bit generator and error detection correction logic. when the edc is enabled, the check bit generator will generate 8 syndrome bits on the 8-byte boundary. the 8 syndrome bits are written into the ddr sdram along with the data. the sfc will burst write two cycles for data, and one cycle for syndrome bits. in order to minimize overhead and increase throughput, not all memory in the ddr sdram is utilized. table 5 lists the total usable memory for all 7 configurations when the edc is enabled. when a read operation is performed, the syndrome bits will be transferred to the error detection correction logic block and decoded to determine whether there are any single bit errors on the data. single bit errors will be corrected and data is passed through to the qp cache. the edc is enabled using the mic[2:0] pins. when the edc is enabled, the dynamics of the total usable memory in the ddr sdram and the sfc operating speed will vary, listed in tables 6 and 7. table 8 shows how to enable the edc feature for the 7 configurations edc off edc on configuration 1 mic [2:0] = 000 mic [2:0] = 010 configuration 2 mic [2:0] = 001 mic [2:0] = 011 configuration 3 mic [2:0] = 111 mic [2:0] = 101 configuration 4 mic [2:0] = 100 mic [2:0] = 110 configuration 5 mic [2:0] = 000 mic [2:0] = 010 configuration 6 mic [2:0] = 100 mic [2:0] = 110 configuration 7 mic [2:0] = 111 mic [2:0] = 101 table 8 ? mic[2:0] configurations
21 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 setting the memory interface signals the configurations listed in figure 2a-2g can be programmed into the sequential flow-control device by using the mic[2:0], mtype[1:0], and mspeed. for information about these signals, please refer to the signal description section. table 9 is a list that shows the settings for the different configurations. mic[2:0] mtype[1:0] mspeed configuration 1 000 - edc off 00 - (4mb x 32) 0 - 133mhz 010 - edc on 10 - (8mb x 32) 1 - 166mhz configuration 2 001 - edc off ? 0 - 133mhz 011 - edc on 11 - (16mb x 16) 1 - 166mhz configuration 3 111 - edc off 00 - (4mb x 32) 0 - 133mhz 101 - edc on 10 - (8mb x 32) 1 - 166mhz configuration 4 110 - edc off 00 - (4mb x 32) 0 - 133mhz 100 - edc on 10 - (8mb x 32) 1 - 166mhz configuration 5 000 - edc off ? 0 - 133mhz 010 - edc on 11 - (16mb x 16) 1 - 166mhz configuration 6 110 - edc off ? 0 - 133mhz 100 - edc on 11 - (16mb x 16) 1 -166mhz configuration 7 111 - edc off ? 0 - 133mhz 101 - edc on 11 - (16mb x 16) 1 - 166mhz table 9 ? memory configurations settings
22 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 functional descriptions master reset and device configuration during master reset the sequential flow-control configuration and settings are determined, this includes the following: 1. synchronous or asynchronous read and write port operation 2. bus-width configuration 3. default offset register values 4. idt standard or first word fall through (fwft) timing mode 5. depth expansion in idt standard or fwft mode 6. i/o voltage set to 2.5v or 3.3v levels 7. jtag function enabled or disabled 8. configuration of the external memory interface the state of the configuration inputs during master reset will determine which of the above modes are selected. a master reset comprises of pulsing the mrs input pin from high to low for a period of time (t rs ) with the configuration inputs held in their respective states. table 10, device configuration summarizes the configuration modes available during master reset. these signals are described in detail in the signal description section. programmable almost empty/almost full flags the sfc has a set of programmable flags ( pae / paf ) that can be used as an early indicator for the empty and full boundary conditions. these flags have an offset value (n, m) that will determine the almost empty and almost full boundary conditions. there are four default offset values selectable during master reset, these values are shown in table 11, default programmable flag offsets. offset values can also be programmed using the serial programming pins (sclk, si, and swen ). the sfc has two internal offset registers that are used to store the specific offset value, one for the pae and one for the paf . the total number of bits (shown in table 12, number of bits required for offset registers) must be completely programmed to the offset registers. the serial programming sequence begins by writing data into the pae register followed by the paf register. see figure 29, serial loading of programmable flag registers for the associated timing diagram. the total number of bits required to program the offset registers will vary depending on the type of configuration that is shown in figure 2a-2g, the bus-width selected, and whether edc is used. the values of n, m are used such that the pae will become active (low) when there are at least one to n words written in the device. similarly paf will become active (low) when there are at least d ? m words or more in the device, where d is the density of the sfc. write port bus-width x48 x24 x12 edc on edc off edc on edc off edc on edc off configuration 1 (128mb) 21 22 22 23 23 24 configuration 1 (256mb) 22 23 23 24 24 25 configuration 2 (256mb) 22 23 23 24 24 25 configuration 3 (256mb) 22 23 23 24 24 25 configuration 3 (512mb) 23 24 24 25 25 26 configuration 4 (256mb) 22 22 23 23 24 24 configuration 4 (512mb) 23 23 24 24 25 25 configuration 5 (512mb) 23 24 24 25 25 26 configuration 6 (768mb) 24 24 25 25 26 26 configuration 7 (1gb) 24 25 25 26 26 27 table 12? number of bits required for offset registers table 10 ? device configuration signal pins static state configuration asyr 0 read port configured in asynchronous mode 1 read port configured in synchronous mode asyw 0 write port configured in asynchronous mode 1 write port configured in synchronous mode bm[3:0] ? see table 13 - bus-matching configurations fsel[1:0] 00 programmable flag register offset value = 127 01 programmable flag register offset value = 1,023 10 programmable flag register offset value = 4,095 11 programmable flag register offset value = 16,383 fwft 0 idt standard mode 1 fwft mode idem 0 depth expansion in fwft mode 1 depth expansion in idt standard mode iosel 0 i/o voltage set to 3.3v levels 1 i/o voltage set to 2.5v levels jsel 0 jtag function is disabled 1 jtag function is enabled mic[2:0] ? see table 8 - mic[2:0] configurations for description mspeed 0 external memory interface clocks set to 133mhz 1 external memory interface clocks set to 166mhz mtype[1:0] 00 external memory configuration is: 4m x 32 01 not used 10 external memory configuration is: 8m x 32 11 external memory configuration is: 16m x 16 fsel1 fsel0 offset n,m 0 0 127 0 1 1,023 1 0 4,095 1 1 16,383 table 11? default pr ogrammable flag offsets
23 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 signal descriptions inputs data inputs (d 0 - d 47 ) data inputs for 48-bit wide data (d 0 - d 47 ), data inputs for 24-bit wide data (d 0 - d 23 ) or data inputs for 12-bit wide data (d 0 - d 11 ). controls master reset ( mrs ) a master reset is accomplished whenever the mrs input is toggled low then high. this operation sets the internal read and write pointers to the first location of the ram array. pae will go low, paf will go high. if fwft is low during master reset then the idt standard mode, along with ef and ff are selected. ef will go low and ff will go high. if fwft is high, then the first word fall through mode (fwft), along with ir and or , are selected. or will go high and ir will go low. all configuration control signals must be set prior to the low to high transition of mrs . during a master reset, the output register is initialized to all zeroes. a master reset is required after power up, before a write operation can take place. mrs is an asynchronous function. see figure 6, master reset and initialization , for the relevant timing diagram. partial reset ( prs ) a partial reset is accomplished whenever the prs input is toggled low then high. as in the case of the master reset, the internal read and write pointers are set to the first location of the ram array, pae goes low, and paf goes high. whichever mode is active at the time of partial reset, idt standard mode or first word fall through, that mode will remain selected. if the idt standard mode is active, then ff will go high and ef will go low. if the first word fall through mode is active, then or will go high, and ir will go low. following partial reset, all values held in the offset registers remain unchanged. the output register is initialized to all zeroes. prs is asynchronous. a partial reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. see figure 7, partial reset , for the relevant timing diagram. asynchronous write ( asyw ) the write port can be configured for either synchronous or asynchronous mode of operation. if during master reset the asyw input is low, then asynchronous operation of the write port will be selected. during asynchronous operation of the write port the wclk input becomes wr input, this is the asynchronous write strobe input. a rising edge on wr will write data present on the data inputs into the sequential flow-control device (sfc). ( wen must be low when using the write port in asynchronous mode). when the write port is configured for asynchronous operation the device must be operating on idt standard mode, fwft mode is not permissable. the full flag ( ff ) and programmable almost full flag ( paf ) operates in an asynchronous manner, that is, the full flag and paf flag will be updated based in both a write operation and read operation. note, if asynchronous mode is selected, fwft is not permissible. refer to figure 24, asynchronous write and pae flag ? idt standard mode and figure 25, asynchronous write and paf flag ? idt standard mode for relevant timing and operational waveforms. asynchronous read ( asyr ) the read port can be configured for either synchronous or asynchronous mode of operation. if during a master reset the asyr input is low, then asynchronous operation of the read port will be selected. during asynchronous operation of the read port the rclk input becomes rd input, this is the asynchronous read strobe input. a rising edge on rd will read data from the sfc via the output register and data output port. ( ren must be tied low during asynchronous operation of the read port). the oe input provides three-state control of the qn output bus, in an asynchronous manner. when the read port is configured for asynchronous operation the device must be operating on idt standard mode, fwft mode is not permissible if the read port is asynchronous. the empty flag ( ef ) and programmable almost empty flag ( paf ) operates in an asynchronous manner, that is, the empty flag and pae will be updated based on both a read operation and a write operation. refer to figure 23, asynchronous read and paf flag ? idt standard mode , figure 26, asynchronous empty boundary ? idt standard mode , figure 27, asynchronous full boundary ? idt standard mode ,, and figure 28, asyn- chronous read and pae flag ? idt standard mode , for relevant timing and operational waveforms. first word fall through ( fwft ) during master reset, the state of the fwft input determines whether the device will operate in idt standard mode or first word fall through (fwft) mode. if, at the time of master reset, fwft is low, then idt standard mode will be selected. this mode uses the empty flag ( ef ) to indicate whether or not there are any words present in the sfc. it also uses the full flag function ( ff ) to indicate whether or not the sfc has any free space for writing. in idt standard mode, every word read from the sfc, including the first, must be requested using the read enable ( ren ) and rclk. if, at the time of master reset, fwft is high, then fwft mode will be selected. this mode uses output ready ( or ) to indicate whether or not there is valid data at the data outputs (q n) . it also uses input ready ( ir ) to indicate whether or not the sfc has any free space for writing. in the fwft mode, the first word written to an empty sfc goes directly to q n after three rclk rising edges, ren = low is not necessary. subsequent words must be accessed using the read enable ( ren ) and rclk. write strobe and write clock (wr/wclk) if synchronous operation of the write port has been selected via asyw , this input behaves as wclk. a write cycle is initiated on the rising edge of the wclk input. data setup and hold times must be met with respect to the low-to-high transition of the wclk. it is permissible to stop the wclk. note that while wclk is idle, the ff / ir , and paf flags will not be updated. the write and read clocks can either be independent or coincident. if asynchronous operation has been selected this input is wr (write strobe). data is asynchronously written into the sfc via the dn inputs whenever there is a rising edge on wr. in this mode the wen input must be low. write enable ( wen ) when the wen input is low, data may be loaded into the sfc on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read operation. when wen is high, no new data is written in the sfc. to prevent data overflow in the idt standard mode, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high allowing a write to occur. the ff is updated by two wclk cycles + t skew after the rclk cycle.
24 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 to prevent data overflow in the fwft mode, ir will go high, inhibiting further write operations. upon the completion of a valid read cycle, ir will go low allowing a write to occur. the ir flag is updated by two wclk cycles + t skew after the valid rclk cycle. wen is ignored when the sfc is full in either fwft or idt standard mode. if asynchronous operation of the write port has been selected, then wen must be held active. read strobe and read clock (rd/rclk) if synchronous operation of the read port has been selected via asyr , this input behaves as rclk. a read cycle is initiated on the rising edge of the rclk input. data can be read on the outputs, on the rising edge of the rclk input. it is permissible to stop the rclk. note that while rclk is idle, the ef / or and pae flags will not be updated. the write and read clocks can be independent or coincident. if asynchronous operation has been selected this input is rd (read strobe). data is asynchronously read from the sfc whenever there is a rising edge on rd. in this mode the ren and rcs inputs must be tied low. the oe input is used to provide asynchronous control of the three-state qn outputs. write chip select ( wcs ) the wcs disables all write data operations (data only) if it is held high. to perform normal operations on the write port, the wcs must be enabled, held low. read enable ( ren ) when read enable is low, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and then no new data is loaded into the output register. the data outputs q 0 -q n maintain the previous data value. in the idt standard mode, every word accessed at q n , including the first word written to an empty cache, must be requested using ren provided that rcs is low. when the last word has been read from the sfc, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the sfc is empty. once a write is performed, ef will go high allowing a read to occur. the ef flag is updated by two rclk cycles + t skew after the valid wclk cycle. both rcs and ren must be active, low for data to be read out on the rising edge of rclk. in the fwft mode, the first word written to an empty sfc automatically goes to the outputs q n , on the third valid low-to-high transition of rclk + t skew after the first write. ren and rcs do not need to be asserted low for the first word to fall through to the output register. in order to access all other words, a read must be executed using ren and rcs . the rclk low-to-high transition after the last word has been read from the sfc, output ready ( or ) will go high with a true read (rclk with ren = low; rcs = low), inhibiting further read operations. ren is ignored when the sfc is empty. if asynchronous operation of the read port has been selected, then ren must be held active, (low). output enable ( oe ) when output enable is enabled (low), the parallel output buffers receive data from the output register. when oe is high, the output data bus (q n ) goes into a high impedance state. during master or a partial reset the oe is the only input that can place the output bus qn, into high-impedance. during reset the rcs input can be high or low, it has no effect on the qn outputs. read chip select ( rcs ) the read chip select input provides synchronous control of the read output port. when rcs goes low, the next rising edge of rclk causes the qn outputs to go to the low-impedance state. when rcs goes high, the next rclk rising edge causes the qn outputs to return to high z. during a master or partial reset the rcs input has no effect on the qn output bus, oe is the only input that provides high-impedance control of the qn outputs. if oe is low the qn data outputs will be low-impedance regardless of rcs until the first rising edge of rclk after a reset is complete. then if rcs is high the data outputs will go to high- impedance. the rcs input does not effect the operation of the flags. for example, when the first word is written to an empty sfc, the ef will still go from low to high based on a rising edge of rclk , regardless of the state of the rcs input. also, when operating the sfc in fwft mode the first word written to an empty sfc will still be clocked through to the output register based on rclk, regardless of the state of rcs . for this reason the user must take care when a data word is written to an empty sfc in fwft mode. if rcs is disabled when an empty sfc is written into, the first word will fall through to the output register, but will not be available on the qn outputs which are in high-z. the user must take rcs active low to access this first word, place the output bus in low-z. ren must remain disabled high for at least one cycle after rcs has gone low. a rising edge of rclk with rcs and ren active low, will read out the next word. care must be taken so as not to lose the first word written to an empty sfc when rcs is high. see figure 15 for read chip select. if asynchronous operation of the read port has been selected, then rcs must be held active, (tied low). oe provides three-state control of qn. bus-matching (bm[3:0]) these pins are used to define the input and output bus widths. during master reset, the state of these pins is used to configure the device bus sizes. all flags will operate on the word/byte size boundary as defined by the selection of bus width. see figures 17-20 for bus-matching configurations . see table 13, bus- matching configurations for the available configurations. bm3 bm2 bm1 bm0 read bus write bus width width 1 0 0 0 x48 x48 1 0 0 1 x24 x48 1 1 0 1 x12 x48 1 0 1 1 x48 x24 1 1 1 1 x48 x12 0 0 0 1 x24 x24 0 1 0 1 x12 x24 0 0 1 1 x24 x12 0 1 1 1 x12 x12 table 13 ? bus-matchings flag select (fsel[1:0]) during master reset, these inputs will select one of four default values for the programmable flags pae and paf . the selected value (listed in table 14 - mtype[1:0] configurations) will apply to both pae and paf offset.
25 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 memory configuration (mic[2:0]) these signals enable the edc feature of the device. see table 8, mic[2:0] configurations for more information. memory speed (mspeed) this pin is used to determine the memory interface clock speed (ck and ck ) for the external memory used. if mspeed is high, external memory ck and ck will be operating at 166mhz. if mspeed is low, then the external memory ck and ck will be operating at 133mhz. master clock (mclk) 33mhz reference clock used to generate ck and ck for external memory interface. memory type (mtype[1:0]) these signals select the density configuration of the external ddr sdram used. see table 14, mtype[1:0] configurations for selection of the memory density configuration. modes. see figure 29, serial loading of programmable flag registers, for the timing diagram. i/o vddq select (iosel) this input determines whether the inputs and outputs will tolerate a 2.5v or 3.3v voltage signals. if iosel is high, then all i/os will be 2.5v levels. if iosel is low, then all i/os will be 3.3v levels. see table 15, parameters affected by i/o selection for a list of affected i/o signals. depth expansion mode select (idem) this select pin is used for depth expansion configuration in idt standard mode. if this pin is tied high, then the ff / ir signal will be inverted to provide a seamless depth expansion interface. if this pin is tied low, the depth expansion in idt standard mode will be deactivated. for details on depth expansion configuration, see figure 34, depth expansion configuration in idt standard mode and figure 35, depth expansion configuration in fwft mode . serial read enable ( sren ) the serial read enable input is an enable used for reading the value of the programmable offset registers. by setting the jsel pin to low, the serial data output (so) and serial clock (sclk) signals can be used with sren to program the offset registers. when sren is low, data at the so can be read from the offset register, one bit for each low-to-high transition of sclk. when serial read enable is high, the reading of the offset registers will stop. sren must be kept low in order to read the entire contents of the scan out register. if at any point sren is toggled high, the read pointer of the offset registers will reset to the first location. the next time sren is enabled the first contents in the offset register will be read back. serial read enable functions the same way in both idt standard and fwft modes. see figure 30, reading of programmable flag registers, for the timing diagram. serial write enable ( swen ) the serial write enable input is an enable used for serial programming of the programmable offset registers. by setting the jsel pin to low, the serial input (si) and serial clock (sclk) signals can be used with swen to program the offset registers. when swen is low, data at the si input are loaded into the offset register, one bit for each low-to-high transition of sclk. when swen is high, the offset registers retain the previous settings and no offsets are loaded. serial write enable functions the same way in both standard idt and fwft density configurations 4m x 32 8m x 32 reserved 16m x 16 mtype0 00 11 mtype1 01 01 table 14 ? mtype[1:0] configurations jtag select (jsel) this input determines whether the jtag port will be activated or deactivated. if jsel is high, then the jtag port is activated and the associated jtag pins (tck, tdi, tdo, tms) are used for the boundary-scan function. if jsel is low, the jtag port is disabled and the serial programming pins (sclk, si, so) will be used to program and read the offset register values for pae and paf . see figure 29 and 30, serial loading and reading of programmable registers for information on how to program the registers. outputs full flag/input ready ( ff / ir ) this is a dual purpose pin. in idt standard mode, the full flag ( ff ) function is selected. when the sfc is full, ff will go low, inhibiting further write operations. when ff is high, the sfc is not full. if no reads are performed after a reset (either mrs or prs ), ff will go low see figure 12, full boundary - idt standard mode , for the relevant timing information. in fwft mode, the input ready ( ir ) function is selected. ir goes low when memory space is available for writing in data. when there is no longer any free space left, ir goes high, inhibiting further write operations. if no reads are performed after a reset (either mrs or prs ), ir will go high see figure 9 write first word cycles - fwft mode , for the relevant timing information. the ir status not only measures the contents of the sfc memory, but also counts the presence of a word in the output register. thus, in fwft mode, the total number of writes necessary to de-assert ir is one greater than needed to assert ff in idt standard mode. ff / ir is synchronous and updated on the rising edge of wclk. ff / ir are double register-buffered outputs. table 15 ? parameters affected by i/o selection sfc i/o affected by i/o selection ddr sdram i/o - not affected (1) asyr mic[2:0] rcs a[12:0] dq[63:0] asyw mclk ren ba[1:0] dqs[7:0] bm[3:0] mrs sren ck ras d[47:0] mspeed swen ck we ef / or mtype[1:0] tck/sclk cas ff / ir oe tdi/si fsel[1:0] pae tdo/so fwft paf tms idem prs wclk/wr iosel q[47:0] wcs jsel rclk/rd wen note : 1. i/o to ddr sdram is not affected by i/o voltage selection
26 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 empty flag ( ef / or ) this is a dual purpose pin. in the idt standard mode, the empty flag ( ef ) function is selected. when the sfc is empty, ef will go low, inhibiting further read operations. when ef is high, the sfc is not empty. figure 10, empty boundary ? idt standard mode for the relevant timing information. in fwft mode, the output ready ( or ) function is selected. or goes low at the same time that the first word written to an empty sfc appears valid on the outputs. or stays low after the rclk low to high transition that shifts the last word from the sfc to the outputs. or goes high only with a true read (rclk with ren = low). the previous data stays at the outputs, indicating the last word was read. further data reads are inhibited until or goes low again. see figure 11, empty boundary (fwft mode) , for the relevant timing information. ef / or is synchronous and updated on the rising edge of rclk. in idt standard mode, ef is a double register-buffered output. in fwft mode, or is a triple register-buffered output. programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when the sfc reaches the almost-full condition. in idt standard mode, if no reads are performed after reset ( mrs ), paf will go low after (d - m) words are written to the sfc. see figure 22, synchronous paf flag - idt standard mode and fwft mode , for the relevant timing information. if asynchronous paf configuration is selected, the paf is asserted low on the low-to-high transition of the write clock (wclk). paf is reset to high on the low-to-high transition of the read clock (rclk). if synchronous paf configuration is selected, the paf is updated on the rising edge of wclk. programmable almost-empty flag ( pae ) the programmable almost-empty flag ( pae ) will go low when the sfc reaches the almost-empty condition. in idt standard mode, pae will go low when there are n words or less in the sfc. the offset ?n? is the empty offset value. the default setting for this value is in table 10, device configuration. in fwft mode, the pae will go low when there are n+1 words or less in the sfc. see figure 21, synchronous pae flag - idt standard mode and fwft mode , for the relevant timing information. if asynchronous pae configuration is selected, the pae is asserted low on the low-to-high transition of the read clock (rclk). pae is reset to high on the low-to-high transition of the write clock (wclk). if synchronous pae configuration is selected, the pae is updated on the rising edge of rclk. data outputs (q 0 -q 47 ) (q 0 -q 47 ) are data outputs for 48-bit wide data, (q 0 - q 23 ) are data outputs for 24-bit wide data or (q 0 -q 11 ) are data outputs for 12-bit wide data. memory clock output (ck) these signals are to be connected to the external ddr sdram's clock input. memory clock output inverted ( ck ) these signals are to be connected to the external ddr sdram's differential clock input. memory bank address input bit (ba[1:0]) these signals are to be connected to the external ddr sdram's bank address input bits. memory column address strobe ( cas ) these signals are to be connected to the external ddr sdram's column address strobe input. memory address bus (a[12:0]) these signals are to be connected to the external ddr sdram's address bus. memory write enable ( we ) these signals are to be connected to the external ddr sdram's write enable. memory row address strobe ( ras ) these signals are to be connected to the external ddr sdram's row address strobe input. bi-directional i/o memory data inputs/outputs dq[63:0] these signals are to be connected to the external ddr sdram's data input bus. memory data strobe output dqs[7:0] these signals are to be connected to the external ddr sdram's data strobe inputs.
27 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 symbol rating com'l & ind'l unit v term terminal voltage ?0.5 to +3.6 (2) v with respect to gnd t stg storage temperature ?55 to +125 c t jmax maximum junction temp. 150 c i out dc output current ?50 to +50 ma symbol parameter industrial/ unit commercial jc junction to case thermal resistance 3.8 c/w ja junction to air thermal resistance c/w airflow @ 0m/s 27.4 @ 1m/s 22.8 @ 2m/s 20.3 @ 3m/s 19.5 @ 4m/s 18.2 @ 5m/s 17.8 msl moisture sensitivity level 3 absolute maximum ratings package thermal data notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. compliant with jedec jesd8-5. v cc terminal only. symbol parameter (1) conditions max. unit c in (2,3) input v in = 0v 10 (3) pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. 3. c in for vref is 20pf. device characteristics recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 2.375 2.5 2.625 v av cc analog supply voltage 2.375 2.5 2.625 v v ddq output rail voltage for i/os 2.375 ? 3.45 v gnd supply ground 0 0 0 v v ref (1) sstl_2 voltage reference input 1.13 1.25 1.38 v t a operating temperature (commercial) 0 ? 70 c t a operating temperature (industrial) -40 ? 85 c note: 1. typically the value of v ref is expected to be (0.49-0.51) x v cc .
28 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 dc electrical characteristics (commercial: v cc = 2.5v 0.125v, t a = 0 c to +70 c;industrial: v cc = 2.5v 0.125v, t a = -40 c to +85 c) general dc test conditions measurements taken with v cc = 2.625v, oe = high, wclk = rclk = 16.7mhz, mclk = 33.3mhz data toggles alternately at 1/2 wclk and rclk frequency 0.4 < v in < v cc , 0.4 < v out < v cc outputs are unloaded (i out = 0) notes : 1. these parameters are compliant under jedec standard for sstl_2 (jesd8-9a). these parameters are classified as sstl_2 class i output buffers under section 3.2.1 of jesd8-9a. 2. i cc (active current) is measured with mclk = 33.3mhz, rclk = wclk = 16.7mhz, and alternate 101010 data pattern toggling on the out puts. 3. i sb (standby current) is measured with mclk = rclk = wclk = 0mhz with no output data toggling. 4. v sdref is the v ref of the ddr sdram. it is not to be confused with the v ref of the sfc. 5. the maximum value may not represent the maximum current dissipated from the sfc. i cc values are dependent upon various factors that include: v cc , temperature, capacitive load, frequency, bus-width, and output switching characteristics. for calculating i cc with specific parameters, please contact idt technical support for assistance. i/o type symbol parameter min. max. unit sfc input i li input leakage current -10 10 a (lvttl) v ih input high voltage v ddq = 3.3v 2.0 5.5 v v ddq = 2.5v 1.7 3.45 v v il input low voltage v ddq = 3.3v ? 0.8 v v ddq = 2.5v -0.3 0.7 v sfc output i lo output leakage current -10 10 a (lvttl) v oh read/write interface output logic ?1? voltage with i oh1 v ddq = 3.3v v ddq ? 0.4 ? v v ddq = 2.5v v ddq ? 0.4 ? v v ol read/write interface output logic ?0? voltage with i ol1 v ddq = 3.3v ? 0.4 v v ddq = 2.5v ? 0.4 v i oh read/write interface output high current (source current) v ddq = 3.3v -2 ? ma v ddq = 2.5v -8 ? ma i ol read/write interface output low current (sink current) v ddq = 3.3v 8 ? ma v ddq = 2.5v 8 ? ma ddr sdram i oh memory interface output high current (source current) -7.6 ? ma i/o (sstl_2) (1) i ol memory interface output low current (sink current) 7.6 ? ma v ih memory interface input high voltage 1.7 3.0 v v il memory interface input low voltage -0.3 0.7 v v oh memory interface output high voltage 1.5 ? v v ol memory interface output low voltage ? 1.00 v symbol parameter min. max. unit i cc1 (2) active v cc current ? 650 ma i cc2 (2) active av cc current ? 18 ma i cc3 (2) active v ddq current ? 1 ma i sb1 (3) standby v cc current ? 600 ma i sb2 (3) standby v ddq current ? 1 ma power consumption
29 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 ac test loads figure 5b. lumped capacitive load, typical derating figure 5a. ac test load input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels 1.25v output reference levels 1.25v 2.5v lvttl ac test conditions input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v 3.3v lvttl ac test conditions 6358 drw13 50 ? v ddq /2 i/o z 0 = 50 ? 10pf 6358 drw13a 6 5 4 3 2 1 20 30 50 80 100 200 capacitance (pf) ? t cd (typical, ns) ac test conditions input pulse levels gnd to 2.5v input rise/fall times 1ns input timing reference levels 1.25v output reference levels 1.25v 2.5v sstl ac test conditions
30 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 ac electrical characteristics (1) ? synchronous timing (commercial: v cc = 2.5v 5%, t a = 0 c to +70 c;industrial: v cc = 2.5v 5%, t a = -40 c to +85 c) notes: 1. all ac timings apply to both standard idt mode and first word fall through mode. 2. industrial temperature range product for the 10ns speed grade is available as a standard device. all other speed grades are a vailable by special order. 3. to achieve 166mhz read and write port operation, the input and/or output bus must be configured to x24 or x18. commercial com?l & ind?l (2) idt72t6480l7-5 idt72t6480l10 (x24 or x12 i/o width only) (3) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit f s synchronous clock cycle frequency ? 166 ? 133 ? 100 mhz t a data access time 1 4 1 5 1 6.5 ns t clk clock cycle time 6 ? 7.5 ? 10 ? ns t clkh clock high time 2.7 ? 3.5 ? 4.5 ? ns t clkl clock low time 2.7 ? 3.5 ? 4.5 ? ns t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t rs reset pulse width 10 ? 10 ? 10 ? ns t rsu reset setup time 15 ? 15 ? 15 ? ns t rsh reset hold time 10 ? 10 ? 10 ? ns t pl reset to pll lock 20 ? 20 ? 20 ? s t rsf reset to flag and output ? 15 ? 15 ? 15 ns t ohz output enable to high-z 1 4 1 5 1 6.5 ns t oe output enable valid 1 4 1 5 1 6.5 ns f mc master clock cycle frequency 32 34 32 34 32 34 mhz t mcyc master clock cycle time 29.4 31.3 29.4 31.3 29.4 31.3 ns t mckh master clock cycle high 0.45 0.55 0.45 0.55 0.45 0.55 t mcyc t mckl master clock cycle low 0.45 0.55 0.45 0.55 0.45 0.55 t mcyc f sc serial clock cycle frequency ? 10 ? 10 ? 10 mhz t sclk serial clock cycle 100 ? 100 ? 100 ? ns t sclkh serial clock high 45 ? 45 ? 45 ? ns t sclkl serial clock low 45 ? 45 ? 45 ? ns t sds serial data setup 15 ? 15 ? 15 ? ns t sdh serial data hold 5 ? 5 ? 5 ? ns t sens serial enable setup 5 ? 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? 5 ? ns t aso serial output data access time ? 20 ? 20 ? 20 ns t wffs write clock to synchronous ff / ir ? 4 ? 5 ? 6.5 ns t refs read clock to synchronous ef / or ? 4 ? 5 ? 6.5 ns t pafs wclk to synchronous paf ? 4 ? 5 ? 6.5 ns t paes rclk to synchronous pae ? 4 ? 5 ? 6.5 ns t skew1 skew time between rclk & wclk for ef / or and ff / ir in sdr 4 ? 5 ? 7 ? ns t skew2 skew time between rclk and wclk for pae / paf 5?7?10?ns t wcss wcs setup time 2 ? 2.5 ? 3.5 ? ns t wcsh wcs hold time 0.5 ? 0.5 ? 0.5 ? ns f c1 memory clock cycle frequency at 166mhz 160 170 160 170 ? ? mhz f c2 memory clock cycle frequency at 133mhz 128 136 128 136 128 136 mhz t ck1 memory clock cycle time at 166mhz 6.2 5.9 ? ? ? ? ns t ck2 memory clock cycle time at 133mhz 7.8 7.3 7.8 7.3 7.8 7.3 ns t ckh1 memory clock cycle high at 166mhz 0.45 0.55 ? ? ? ? t ck1 t ckh2 memory clock cycle high at 133mhz 0.45 0.55 0.45 0.55 0.45 0.55 t ck2 t ckl1 memory clock cycle low at 166mhz 0.45 0.55 ? ? ? ? t ck1 t ckl2 memory clock cycle low at 133mhz 0.45 0.55 0.45 0.55 0.45 0.55 t ck2
31 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 ac electrical characteristics ? asynchronous timing (commercial: v cc = 2.5v 5%, t a = 0 c to +70 c;industrial: v cc = 2.5v 5%, t a = -40 c to +85 c) commercial commercial com?l & ind?l (2) idt72t6480l7-5 idt72t6480l7-5 idt72t6480l10 (x24 or x12 i/o width only) (3) symbol parameter min. max. min. max. min. max. unit f a asynchronous clock cycle frequency ? 100 ? 83 ? 50 mhz t aa data access time 0.6 8 0.6 10 1 12 ns t cyc cycle time 10 ? 12 ? 20 ? ns t cych cycle high time 4.5 ? 5 ? 8 ? ns t cycl cycle low time 4.5 ? 5 ? 8 ? ns t ffa rising edge to ff ?8?10?14ns t efa rising edge to ef ?8?10?14ns t pafa rising edge to paf ?8?10?14ns t paea rising edge to pae ?8?10?14ns t rpe read pulse after ef high 8 ? 10 ? 14 ? ns notes: 1. all ac timings apply to both standard idt mode and first word fall through mode. 2. industrial temperature range product for the 10ns speed grade is available as a standard device. all other speed grades are a vailable by special order. 3. to achieve 166mhz read and write port operation, the input and/or output bus must be configured to x24 or x18.
32 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 6. master reset and initialization t rsf idt standard mode synchronous read port selected synchronous write port selected if oe = high asynchronous read port selected asynchronous write port selected 2.5v i/o voltage selected mrs ren wen sren swen ef or ff ir ck ck q[47:0] fwft asyr asyw iosel paf pae idem depth expansion in idt standard mode depth expansion in fwft standard mode t rsu t rsu t rsu t rsu t rsf t rsu t rsf if oe = low t pl t pl t pl t pl t rsu t rsu t rsu 3.3v i/o voltage selected the clock may not be locked to the required operating frequency before t pl the clock may not be locked to the required operating frequency before t pl t rs t rsf t rh t rh t rh t rh t rsu 6358 drw14 fwft mode if fwft mode is selected if idt mode is selected if fwft mode is selected if idt mode is selected note: 1. for other signals that are latched during master reset, refer to master reset and device configuration section. symbol parameter min. max. unit t rs reset pulse width 10 ? ns t rsu reset setup time 15 ? ns t rsh reset hold time 10 ? ns t pl reset to pll lock 20 ? s t rsf reset to flag and output ? 15 ns
33 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 7. partial reset if oe = high prs ren wen sren swen ef or ff ir if oe = low t rs t rsu 6358 drw15 t rh t rsu t rh t rsu t rh t rsu t rh t rsf t rsf if idt mode is selected if fwft mode is selected if idt mode is selected if fwft mode is selected q[47:0] paf pae t rsf t rsf t rsf t rsf symbol parameter min. max. unit t rs reset pulse width 10 ? ns t rsu reset setup time 15 ? ns t rsh reset hold time 10 ? ns t pl reset to pll lock 20 ? s t rsf reset to flag and output ? 15 ns
34 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 8. write first word cycles - idt standard mode t ens 12 t a word 0 t a t ens t skew1 word 0 t enh wclk ren wen d[47:0] rclk 6358 drw16 ef q[47:0] t refs t enh word 1 word 2 t enh t refs t a word 1 word 2 t ens notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. figure 9. write first word cycles - fwft mode 12 3 t a word 0 t a t ens t skew1 word 0 t enh wclk ren wen d[47:0] rclk 6358 drw17 or q[47:0] t refs t ens t enh word 1 word 2 t enh t refs t a word 1 word 2 t ens notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1000, fwft = high, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t sens serial enable setup 5 ? 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? 5 ? ns t a data access time 1 4 1 5 1 6.5 ns t skew1 skew time between rclk and wclk for ef / or 4?5?7?ns and ff / ir in sdr t refs read clock to synchronous ef / or ? 4 ? 5 ? 6.5 ns
35 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 10. empty boundary - idt standard mode no operation rclk ren 6358 drw18 ef t clk t clkh t clkl t enh t ref t a t oe q[47:0] oe wclk (1) t skew1 wen d[47:0] t ens t ens t enh t ds t dh word 0 1 2 t olz no operation last word word 0 t ens t enh t ds t dh t ohz last word t ref t enh t ens t a t a t ref t ens t enh word 1 word 1 notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: rcs = low, wcs = low, bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. figure 11. empty boundary - fwft mode 12 3 t a t a last word - 2 rclk ren or wclk 6358 drw19 wen d[47:0] t ens t enh q[47:0] word 0 t ds t dh last word - 3 t a last word - 1 t refs t skew1 last word t a word 0 t refs notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1000, fwft = high, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t clk clock cycle time 6 ? 7.5 ? 10 ? ns t clkh clock high time 2.7 ? 3.5 ? 4.5 ? ns t clkl clock low time 2.7 ? 3.5 ? 4.5 ? ns t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t refs read clock to synchronous ef / or ? 4 ? 5 ? 6.5 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir in sdr 4 ? 5 ? 7 ? ns
36 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 12. full boundary - idt standard mode 1 2 wclk wen d[47:0] rclk 6358 drw20 ren q[47:0] ff t ds t dh t ens t enh t skew1 t wffs t ens t wffs t a previous word in register word 0 t a word 1 t a word 2 t a word 3 w d-1 w d notes: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high after one wclk cycle (plus t wffs ). if t skew1 is not met, then ff de-assertion may be delayed one extra wclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. 1 2 wclk wen d[47:0] rclk 6358 drw21 ren q[47:0] ir t ds w d-1 t dh t ens t enh t skew1 t wffs t ens t wffs t a word 0 word 1 t a word 2 t a word 3 t a word 4 w d notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: rcs = low, wcs = low, bm[3:0] = 1000, fwft = high, asyr = high, and asyw = high. figure 13. full boundary - fwft mode 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t wffs write clock to synchronous ff / ir ? 4 ? 5 ? 6.5 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir in sdr 4 ? 5 ? 7 ? ns
37 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 14. output enable 6358 drw22 rclk ren q[47:0] oe word 1 word 2 word 3 word 4 t a t a t a t ohz t oe word 4 note: 1. settings: rcs = low, bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. figure 16. write chip select t ens 6358 drw24 word 0 wclk t ds wen d[47:0] wcs word 1 word 2 t dh t wcss t wcsh figure 15. read chip select 6358 drw23 rclk t a ren q[47:0] rcs word 1 t a t a t enh t rcslz t ens word 2 word 3 word 4 word 4 t a t rcshz t ens note: 1. settings: oe = low, bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. note: 1. settings: bm[3:0] = 1000, fwft = low, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t ohz output enable to high-z 1 4 1 5 1 6.5 ns t oe output enable valid 1 4 1 5 1 6.5 ns t wcss wcs setup time 2 ? 2.5 ? 3.5 ? ns t wcsh wcs hold time 0.5 ? 0.5 ? 0.5 ? ns
38 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1111, fwft = low, asyr = high, and asyw = high. figure 17. bus-matching configuration - x48 in to x24 out - idt standard mode figure 18. bus-matching configuration - x48 in to x12 out - idt standard mode 12 t ds t skew1 word 0 t dh t ens t enh wclk ren wen d[47:0] rclk 6358 drw25 ef q[23:0] previous word in register d[47:24] t refs t a word 0 d[23:0] word 0 d[47:24] t a t refs t ens t enh 12 wclk ren wen d[47:0] rclk 6358 drw26 ef q[11:0] previous word in register d[47:36] t ds t skew1 word 0 t dh t ens t refs t ens t enh t a t a t a t a t refs word 0 d[11:0] word 0 d[23:12] word 0 d[35:24] word 0 d[47:36] notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1011, fwft = low, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t refs read clock to synchronous ef / or ? 4 ? 5 ? 6.5 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir in sdr 4 ? 5 ? 7 ? ns
39 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 19. bus-matching configuration - x24 in to x48 out - idt standard mode figure 20. bus-matching configuration - x12 in to x48 out - idt standard mode 1 2 t ds word 0 q[23:0] t dh word 0 q[23:0] wclk ren wen d[23:0] rclk 6358 drw27 t ens t a t refs ef q[47:0] previous word in register word 0 t ds t dh t enh t skew1 t enh t ens t refs t skew1 t a t refs t refs 12 word 0 t enh t ens wclk ren wen d[11:0] rclk 6358 drw28 t ds word 0 q[11:0] t dh t enh t ens word 0 q[23:12] word 0 q[35:24] word 0 q[47:36] ef q[47:0] previous word in register 3 notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1001, fwft = low, asyr = high, and asyw = high. notes: 1. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high after one rclk cycle (plus t refs ). if t skew1 is not met, then ef de-assertion may be delayed one extra rclk cycle. 2. settings: oe = low, rcs = low, wcs = low, bm[3:0] = 1101, fwft = low, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ens enable setup time 2 ? 2.5 ? 3.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t refs read clock to synchronous ef / or ? 4 ? 5 ? 6.5 ns t skew1 skew time between rclk and wclk for ef / or and ff / ir in sdr 4 ? 5 ? 7 ? ns
40 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 21. synchronous pae flag - idt standard mode and fwft mode figure 22. synchronous paf flag - idt standard mode and fwft mode wclk wen d[47:0] rclk ren q[47:0] pae t ds t dh t enh 12 t skew2 t paes 12 t paes n + 1 words or less in memory (2) n words or less in memory (2) n + 2 words or more in memory (2) n + 1 words or more in memory (2) t a t ens t enh word 0 previous word in register word n + 1 6358 drw29 12 1 2 t a t ens t enh t ds t dh wclk wen d[47:0] rclk ren q[47:0] paf word d - m word d - (m + 1) t pa f s d - (m + 1) words or less in memory t pa f s t skew2 t dh previous word in register word 0 d - m words or more in memory 6358 drw30 notes: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that pae will go high after one rclk cycle (plus t paes ). if t skew2 is not met, then pae de-assertion may be delayed one extra rclk cycle. 2. n = pae offset, see table 10 for information on setting pae offset values. 3. settings: oe = low, rcs = low, bm[3:0] = 1000, asyr = high, and asyw = high. notes: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that paf will go high after one rclk cycle (plus t pafs ). if t skew2 is not met, then paf de-assertion may be delayed one extra rclk cycle. 2. m = paf offset, d = density of sfc, see table 11 for information on setting paf offset values. 3. settings: oe = low, rcs = low, bm[3:0] = 1000, asyr = high, and asyw = high. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t enh enable hold time 0.5 ? 0.5 ? 0.5 ? ns t a data access time 1 4 1 5 1 6.5 ns t pafs wclk to synchronous paf ? 4 ? 5 ? 6.5 ns t paes rclk to synchronous pae ? 4 ? 5 ? 6.5 ns t skew2 skew time between rclk and wclk for pae / paf 5?7?10?ns
41 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 23. asynchronous read and paf flag - idt standard mode figure 24. asynchronous write and pae flag - idt standard mode figure 25. asynchronous write and paf flag - idt standard mode t aa 6358 drw31 word d - (m - 1) t aa word d - (m - 2) paf rd q[47:0] word d - m t aa t pa fa word d - (m + 1) d - (m + 1) words or less in memory (d - m) words or more in memory t dh 6358 drw32 n words or less in memory (1) word n - 1 pae wr d[47:0] t paea n + 1 words or more in memory (1) word n t ds t dh t ds word n + 1 t dh t ds d - (m + 1) words or less in memory t dh 6358 drw33 word d - (m + 2) paf wr d[47:0] t pa fa t ds t ds t ds t dh word d - (m + 1) word d - m d - m words or more in memory t dh notes: 1. m = paf offset, see table 10 for information on paf offset values. d = density of sfc. 2. settings: oe = low, rcs = low, bm[3:0] = 1000, fwft = low, asyr = low, and asyw = low. 3. asynchronous read is available in idt standard mode only. notes: 1. m = paf offset, see table 11 for information on paf offset values. d = density of sfc. 2. settings: wcs = low, bm[3:0] = 1000, fwft = low, asyr = low, and asyw = low. 3. asynchronous read is available in idt standard mode only. notes: 1. n = pae offset, see table 11 for information on pae offset values. 2. settings: wcs = low, bm[3:0] = 1000, fwft = low, asyr = low, and asyw = low. 3. asynchronous read is available in idt standard mode only. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t ds data setup time 2 ? 2.5 ? 3.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t aa data access time 0.6 8 0.6 10 1 12 ns t pafa rising edge to paf ?8?10?14ns
42 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 26. asynchronous empty boundary - idt standard mode figure 27. asynchronous full boundary - idt standard mode figure 28. asynchronous read and pae flag - idt standard mode word 0 wr t ds t dh t ds t dh word 1 t cycl t cych t cyc t rpe t efa t efa t aa t aa word 0 word 1 previous word in register ef d[47:0] rd q[47:0] 6358 drw34 previous word in register word 0 t ffa t aa t ffa t dh t ds 6358 drw35 w d wr d[47:0] rd q[47:0] ff t aa 6358 drw36 word n - 2 t aa n words or less in memory (1) word n - 3 pae rd q[47:0] word n - 1 t aa t paea word n n words or more in memory (1) notes: 1. settings: oe = low, rcs = low, wcs = low, fwft = low, asyr = low, and asyw = low. 2. asynchronous read is available in idt standard mode only. notes: 1. settings: oe = low, rcs = low, wcs = low, fwft = low, asyr = low, and asyw = low. 2. asynchronous read is available in idt standard mode only. notes: 1. n = pae offset, see table 11 for information on pae offset values. 2. asynchronous read is available in idt standard mode only. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t aa data access time 0.6 8 0.6 10 1 12 ns t cyc cycle time 10 ? 12 ? 20 ? ns t cych cycle high time 4.5 ? 5 ? 8 ? ns t cycl cycle low time 4.5 ? 5 ? 8 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ds data setup time 2 ? 2.5 ? 3.5 ? ns t efa rising edge to ef ?8?10?14ns t ffa rising edge to ff ?8?10?14ns t paea rising edge to pae ?8?10?14ns t rpe read pulse after ef high 8 ? 10 ? 14 ? ns
43 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 figure 29. serial loading of programmable flag registers (idt standard and fwft modes) sclk swen si 6358 drw37 t senh t sens t ds bit 0 empty offset bit x bit 0 full offset t enh bit x t dh figure 30. reading of programmable flag registers (idt standard and fwft modes) sclk sren sdo 6358 drw38 empty offset full offset t sens t aso t senh bit x t sclk t sckh t sckl bit 0 bit 0 (lsb) bit x (msb) notes: 1. settings: jsel = low. 2. x is the required number of bits to program the pae and paf offset registers. see table 12 for the numbers based on the values external configurations. notes: 1. settings: jsel = low. 2. x is the required number of bits to program the pae and paf offset registers. see table 12 for the numbers based on the values external configurations. 7-5ns 7-5ns 10ns (x24 or x12 i/o only) (x48 i/o width only) symbol parameter min. max. min. max. min. max. unit t dh data hold time 0.5 ? 0.5 ? 0.5 ? ns t ds data setup time 2 ? 2.5 ? 3.5 ? ns t aso serial output data access time ? 20 ? 20 ? 20 ns t sens serial enable setup 5 ? 5 ? 5 ? ns t senh serial enable hold 5 ? 5 ? 5 ? ns t sclk serial clock cycle 10 ? 10 ? 10 ? ns t sclkh serial clock high 45 ? 45 ? 45 ? ns t sclkl serial clock low 45 ? 45 ? 45 ? ns
44 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 t 4 t 3 tdo tdo tdi/ tms tck t do notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tckfall t4 = t tckrise 6358 drw39 t 1 t 2 t tck t dh t ds figure 31. standard jtag timing parameter symbol test conditions min. max. units jtag clock input period t tck - 100 - ns jtag clock high t tckhigh -40-ns jtag clock low t tcklow -40-ns jtag clock rise time t tckrise --5 (1) ns jtag clock fall time t tckfall --5 (1) ns jtag ac electrical characteristics (v cc = 2.5v 5%; tambient (industrial) = 0 c to +85 c) note: 1. 50pf loading on external output signals. note: 1. guaranteed by design. system interface parameters idt72t6480 parameter symbol test conditions min. max. units data output t do (1) -20ns data output hold t doh (1) 0-ns data input t ds t rise=3ns 10 - ns t dh t fall=3ns 10 -
45 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 jtag timing specifications (ieee 1149.1 compliant) the jtag test port in this device is fully compliant with the ieee standard test access port (ieee 1149.1) specifications. four additional pins (tdi, tdo, tms and tck) are provided to support the jtag boundary scan interface. note that idt provides appropriate boundary scan description language program files for these devices. the standard jtag interface consists of seven basic elements: ? test access port (tap) ? tap controller ? instruction register (ir) ? data register port (dr) ? bypass register (byr) ? id code register the following sections provide a brief description of each element. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). the figure below shows the standard boundary-scan architecture figure 32. jtag architecture test access port (tap) the tap interface is a general-purpose port that provides access to the internal jtag state machine. it consists of three input ports (tclk, tms, tdi) and one output port (tdo). the tap controller the tap controller is a synchronous finite state machine that responds to tms and tclk signals to generate clock and control signals to the instruction and data registers for capture and updating of data passed through the tdi serial input. in pad in pad incell incell core logic outcell outcell out pad out pad all outputs all inputs eg: dins, clks (bsdl file describes the chain order) id bypass instruction register ta p tms tdi tck instruction select enable tdo 6358 drw40
46 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 refer to the ieee standard test access port specification (ieee std. 1149.1) for the full state diagram all state transitions within the tap controller occur at the rising edge of the tclk pulse. the tms signal level (0 or 1) determines the state progression that occurs on each tclk rising edge. test-logic-reset all test logic is disabled in this controller state enabling the normal operation of the ic. the tap controller state machine is designed in such a way that, no matter what the initial state of the controller is, the test-logic-reset state can be entered by holding tms at high and pulsing tck five times. run-test-idle in this controller state, the test logic in the ic is active only if certain instructions are present. for example, if an instruction activates the self test, then it will be executed when the controller enters this state. the test logic in the ic is idle otherwise. select-dr-scan this is a controller state where the decision to enter the data path or the select-ir-scan state is made. select-ir-scan this is a controller state where the decision to enter the instruction path is made. the controller can return to the test-logic-reset state other wise. capture-ir in this controller state, the shift register bank in the instruction register parallel loads a pattern of fixed values on the rising edge of tck. the last two significant bits are always required to be ?01?. figure 33. tap controller state diagram shift-ir in this controller state, the instruction register gets connected between tdi and tdo, and the captured pattern gets shifted on each rising edge of tck. the instruction available on the tdi pin is also shifted in to the instruction register. tdo changes on the falling edge of tck. exit1-ir this is a controller state where a decision to enter either the pause- ir state or update-ir state is made. pause-ir this state is provided in order to allow the shifting of instruction register to be temporarily halted. exit2-dr this is a controller state where a decision to enter either the shift- ir state or update-ir state is made. update-ir in this controller state, the instruction in the instruction register scan chain is latched in to the register of the instruction register on every falling edge of tck. this instruction also becomes the current instruction once it is latched. capture-dr in this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of tck. shift-dr, exit1-dr, pause-dr, exit2-dr and update-dr these controller states are similar to the shift-ir, exit1-ir, pause-ir, exit2-ir and update-ir states in the instruction path. test-logic reset run-test/ idle 1 0 0 select- dr-scan select- ir-scan 1 1 1 capture-ir 0 capture-dr 0 0 exit1-dr 1 pause-dr 0 exit2-dr 1 update-dr 1 exit1-ir 1 exit2-ir 1 update-ir 1 1 0 1 1 1 6358 drw41 0 shift-dr 0 0 0 shift-ir 0 0 pause-ir 0 1 input is tms 0 0 1 notes: 1. five consecutive 1's at tms will reset the tap. 2. tap controller resets automatically upon power-up.
47 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 the instruction register the instruction register (ir) is eight bits long and tells the device what instruction is to be executed. information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during capture-dr. test data register the test data register contains three test data registers: the bypass, the boundary scan register and device id register. these registers are connected in parallel between a common serial input and a common serial data output. the following sections provide a brief description of each element. for a complete description, refer to the ieee standard test access port specification (ieee std. 1149.1-1990). test bypass register the register is used to allow test data to flow through the device from tdi to tdo. it contains a single stage shift register for a minimum length in the serial path. when the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of tclk when the tap controller is in the capture-dr state. the operation of the bypass register should not have any effect on the operation of the device in response to the bypass instruction. the boundary-scan register the boundary-scan register (bsr) contains one boundary-scan cell (bsc) for each normal-function input pin and one bsc for each normal-function i/o pin (one single cell for both input data and output data). the bsr is used 1) to store test data that is to be applied externally to the device output pins, and/ or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. the device identification register the device identification register is a read only 32-bit register used to specify the manufacturer, part number and version of the device to be determined through the tap in response to the idcode instruction. idt jedec id number is 0xb3. this translates to 0x33 when the parity is dropped in the 11-bit manufacturer id field. for the idt72t6480, the part number field contains the following values: idt72t6480 jtag device identification register 31(msb) 28 27 12 11 1 0(lsb) version (4 bits) part number (16-bit) manufacturer id (11-bit) 0000 0033 (hex) 1 jtag instruction register the instruction register allows an instruction to be serially input into the device when the tap controller is in the shift-ir state. the instruction is decoded to perform the following: ? select test data registers that may operate while the instruction is current. the other test data registers should not interfere with chip operation and the selected data register. ? define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. the instruction register is a 4 bit field (i.e. ir3, ir2, ir1, ir0) to decode 16 different possible instructions. instructions are decoded as follows. hex instruction function value 0000 extest test external pins 0001 sample/preload select boundary scan register 0002 idcode selects chip identification register 0003 high-impedance puts all outputs in high-impedance state 0008 clamp fix the output chains to scan chain values 000f bypass select bypass register private several combinations are private (for idt internal use). do not use codes other than those identified above. jtag instruction register decoding the following sections provide a brief description of each instruction. for a complete description refer to the ieee standard test access port specification (ieee std. 1149.1-1990). extest the required extest instruction places the device into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. as such, the extest instruction is the workhorse of ieee. std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. sample/preload the required sample/preload instruction allows the device to remain in a normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. during this instruction, the boundary-scan register can be accessed via a data scan operation, to take a sample of the functional data entering and leaving the device. this instruction is also used to preload test data into the boundary-scan register before loading an extest instruction. idcode the optional idcode instruction allows the device to remain in its functional mode and selects the optional device identification register to be connected between tdi and tdo. the device identification register is a 32-bit shift register containing information regarding the device manufacturer, device type, and version code. accessing the device identification register does not interfere with the operation of the device. also, access to the device identification register should be immediately available, via a tap data-scan operation, after power- up of the device or by otherwise moving to the test-logic-reset state. device part# field idt72t6480 0438 (hex)
48 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 clamp the optional clamp instruction sets the outputs of an device to logic levels determined by the contents of the boundary-scan register and selects the one- bit bypass register to be connected between tdi and tdo. before loading this instruction, the contents of the boundary-scan register can be preset with the sample/preload instruction. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the outputs. high-impedance the optional high-impedance instruction sets all outputs (including two-state as well as three-state types) of an device to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between tdi and tdo. during this instruction, data can be shifted through the bypass register from tdi to tdo without affecting the condition of the device outputs. bypass the required bypass instruction allows the device to remain in a normal functional mode and selects the one-bit bypass register to be connected between tdi and tdo. the bypass instruction allows serial data to be transferred through the ic from tdi to tdo without affecting the operation of the device.
49 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 gnd transfer clock fwft fwft wclk wen ff dn idem sfc #1 rclk or ren qn wclk wen ir dn idem sfc #2 rclk ef ren qn v cc v cc write clock write enable full flag data inputs read clock empty flag read enable data outputs 6358 drw42 v cc v cc transfer clock fwft fwft wclk wen ir dn idem sfc #1 rclk or ren qn wclk wen ir dn idem sfc #2 rclk or ren qn gnd gnd write clock write enable input ready flag data inputs read clock output ready flag read enable data outputs 6358 drw43 figure 34. depth expansion configuration in idt standard mode figure 35. depth expansion configuration in fwft mode depth expansion configuration the sequential flow-control (sfc) device can be connected with multiple sfcs in depth expansion to provide additional storage density that?s greater than 1gb. in depth expansion mode, two or mode devices are connected through a common transfer interface, as shown in figure 34. the transfer clock can be a separate free-running clock or driven from the same system write or read clock. in depth expansion configuration, the first word written to an empty configu- ration will pass from the first sfc to the next until it appears on the second (or last) sfc in the chain. if no reads are performed, data will begin accumulating in the second sfc until it is full. once the second sfc is full it will disable the ren to the first sfc. at this point data will begin accumulating in the first sfc. once both devices are full, the entire configuration is full and the full flag indicator will go low. for an empty configuration, the amount of time it takes for the empty flag of the second (or last) sfc in the chain to go low (i.e. valid data available to be read out of the device) after a word has been written into the first fifo is the sum of the delays for each individual sfc: (n - 1) x (4 x transfer clock) + 3 x rclk where n is the number of sfcs in the chain and rclk is the rclk period in ns. this latency is only noticeable for the first word written to an empty configuration. there will be no delay evident for subsequent words written into the chain. in the full configuration, the amount of time it takes for the ff of the first sfc to go from low to high after reading one word from the chain is the sum of the delays for each individual sfc: (n - 1) x (3 x transfer clock) + 2 x wclk depth expansion is available in both idt standard mode and first word fall through (fwft) mode. if idt standard mode is selected, the idem signal needs to be high. if fwft mode is selected, the idem signal needs to be low.
50 idt72t6480 2.5v, sequential flow-control device x12, x24, x48 bit wide configuration commercial and industrial temperature ranges october 10, 2005 width expansion configuration the sequential flow-control (sfc) device can be connected with another sfcs in width expansion to support bus-widths greater than 36-bits. this configuration connects the input and output bus of two devices together to create a wider bus. the read and write clocks for each device are driven with a clock driver. the empty and full flags of both devices are connected to a logic gate (and/or) depending on whether idt standard mode or fwft mode is selected. because of the variation in skew between the read clock and write clock, it is possible for ef / ff deassertion and ir / or assertion to vary from one cycle between the devices. the logic gate connected to the status flags will create a composite flag that will update the status of both sfc devices to represent a more accurate status of the configuration. to minimize the skew between the two write and read clocks, a clock driver (idt5t905 recommended) is used to drive the input clocks for both sfc devices. figure 36 illustrates the width expansion configuration. wclk wen dn rclk ren ef / or qn sfc ff / ir write clock write enable full flag/input ready data inputs read clock empty flag/output ready read enable data outputs 64 36 36 wclk wen dn rclk ren ef / or qn sfc ff / ir gate (1) full flag/input ready gate (1) empty flag/output ready 64 clock driver idt5t905 clock driver idt5t905 write clock read clock clock driver idt5t905 clock driver idt5t905 36 36 6358 drw44 figure 36. width expansion configuration in idt standard mode and fwft mode notes: 1. use an and gate in idt standard mode, an or gate in fwft mode. 2. do not connect any output signals directly together.
51 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1533 san jose, ca 95138 fax: 408-284-2775 email: flow-controlhelp@idt.com www.idt.com ordering information plastic ball grid array (pbga, bb324) commercial (0 c to +70 c) industrial (-40 c to +85 c) low power 6358 drw45 commercial only l idt xxxxx device type x power xx speed x package x process / temperature range blank i (1) 72t6480 2.5v sequential flow-control device configurable to x12, x24, or x48 clock cycle time (t clk ) speed in nanoseconds bb 7-5 10 commercial and industrial datasheet document history 07/29/2004 pgs. 1, 4, 7-11, 13-25, 27-29, 31-43, 47, 49, and 51. 04/11/2005 pg. 10. 04/15/2005 pg. 10 and 51. 06/28/2005 pgs. 16 and 24. 10/10/2005 pgs. 1, 15 and 16.

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